Integrated Scan Driver Stage Circuit for Dual-Level Scan Output
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Solution Overview
Problem
Existing stage circuits for display devices face challenges in efficiently supplying high-level and low-level scan signals simultaneously, which affects the performance and efficiency of organic light emitting display devices.
Innovation Solution
A stage circuit design that includes input and output units to control voltages using shift pulses, clock signals, and power supplies to output high-level and low-level scan signals, with specific transistor and capacitor configurations to manage signal timing and voltage levels, allowing for simultaneous supply of scan signals to scan lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate stages are used for high-level and low-level scan signals, then signal supply reliability is improved, but device complexity and mounting area increase
Solution Approach 1:
The patent combines the functions of high-level scan signal supply and low-level scan signal supply into a single stage circuit. The stage includes a first sub-stage for generating high-level scan signals and a second sub-stage for generating low-level scan signals, both integrated within the same stage structure. This merging reduces the total number of stages required while maintaining the reliability of simultaneous signal supply to pixels using both NMOS and PMOS transistors.
Solution Approach 2:
The single stage circuit is designed to perform multiple functions: it generates both high-level scan signals (for NMOS transistor control) and low-level scan signals (for PMOS transistor control) simultaneously. The stage receives a single input scan signal and produces both signal levels through its internal sub-stages, making it a universal component that replaces what would traditionally require two separate stages.
2Area of stationary object
If single stage supplies both high-level and low-level scan signals, then mounting area is reduced, but signal timing control complexity increases
Solution Approach 1:
The stage is segmented into distinct sub-stages: a first sub-stage for high-level scan signal generation and a second sub-stage for low-level scan signal generation. Each sub-stage has dedicated transistors and capacitors that operate independently to control their respective signal levels. This segmentation within the unified stage structure allows for precise timing control of both signal types without requiring excessive complexity at the overall stage level.
Solution Approach 2:
The patent uses clock signals as intermediary control mechanisms to coordinate the operation of the first and second sub-stages. The clock signal timing and phase relationships mediate the interaction between the two sub-stages, ensuring proper synchronization of high-level and low-level scan signal generation. This intermediary timing control simplifies the overall coordination compared to direct complex inter-stage signaling.
3Ease of manufacture
If conventional stage circuits are used, then manufacturing process is simpler, but performance efficiency of OLED devices decreases
Solution Approach 1:
The stage circuit employs dynamic control through clock signals that actively manage the timing and generation of scan signals. The first and second sub-stages use clocked transistor switching to dynamically generate high-level and low-level scan signals in precise synchronization. This dynamic operation improves the efficiency of OLED pixel activation compared to static or less synchronized conventional circuits, while maintaining compatibility with standard manufacturing processes for display devices.
Data Source
AI summary
A stage circuit including an input unit controlling voltages of a first node and a second node by using a shift pulse or a gate start pulse input to a first input terminal, a first clock signal input to a second input terminal, a second clock signal input to a third input terminal, a first power supply input to a first power supply input terminal and a second power supply input to a second power supply input terminal, and a first output unit receiving a third clock signal from a fourth input terminal and the second power supply from the second power supply input terminal and outputting a high-level scan signal to a first output terminal corresponding to the voltages of the first node and the second node.