Scan Driver Clock Switching for Low-Power Frame Hold
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Solution Overview
Problem
Conventional methods of reducing power consumption in display devices by lowering the driving frequency of scan drivers result in maintaining a fast clock signal during hold times, leading to inefficiencies.
Innovation Solution
A scan driver design that reduces the driving frequency during hold times by using a combination of transistors and capacitors to maintain a constant voltage level, employing a first and second clock signal to supply power from a first and second power source, and includes a stabilizing portion to limit voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the driving frequency of the scan driver is reduced to reduce power consumption, then power consumption is reduced, but the clock signal is maintained at a fast frequency during hold time which causes inefficiency
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable rather than fixed. The clock driving unit dynamically changes the frequency of the clock signal based on the operating phase: using a first frequency during frame time for active scanning and a second (lower) frequency during hold time when no scanning is needed. This dynamic adaptation resolves the contradiction by allowing the system to optimize both power consumption and efficiency at different operational states.
Solution Approach 2:
The patent implements parameter changes by modifying the frequency parameter of the clock signal according to different operational requirements. The system transitions between two frequency states: a higher frequency during active frame time and a lower frequency during hold time. This parameter adjustment enables the clock signal to match the actual processing needs, reducing wasted energy while maintaining productivity when needed.
2Use of energy by moving object
If the clock signal frequency is reduced during hold time, then power consumption is reduced, but the output voltage stability may be affected
Solution Approach 1:
The patent applies preliminary action through the voltage holding unit, which prepares and maintains the output voltage at appropriate levels during hold time before the next frame begins. By pre-establishing the voltage state and using holding capacitors to maintain it, the system ensures voltage stability is preserved even when the clock frequency is reduced, thus resolving the contradiction between power savings and voltage stability.
Solution Approach 2:
The patent introduces intermediary elements (holding capacitors and voltage holding units) that mediate between the reduced clock frequency and the output voltage stability. These intermediaries store energy and maintain voltage levels during hold time, acting as a buffer that decouples the clock frequency reduction from potential voltage instability, allowing both low power consumption and stable output voltage to coexist.
Data Source
AI summary
A scan driver and a driving method thereof, in which the scan driver includes a plurality of stages outputting an output signal in response to clock signals supplied at a first frequency during a driving time of one frame, wherein the plurality of stages are supplied with the clock signals at a second frequency lower than the first frequency during a hold time of the one frame that is separate from the driving time of the one frame.