Scan Driver IC Segmentation for Chip Size Reduction
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Solution Overview
Problem
Conventional scan driver LSI circuits have a large wiring region size due to complex wiring patterns, leading to increased chip size, which hampers efficient assembly and productivity.
Innovation Solution
The integrated circuit for scan driving is designed with odd-numbered and even-numbered output pads, driver circuits, and selection circuits arranged in separate regions, allowing for parallel wiring connections that reduce the wiring region size and overall chip size by eliminating crossing wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex wiring patterns are used to connect scan driver circuits, then all scan lines can be driven, but the wiring region size and chip size increase
Solution Approach 1:
The scan driver LSI is divided into multiple independent scan driver circuits (first scan driver circuit, second scan driver circuit, etc.), each capable of driving a subset of scan lines. This segmentation allows wiring to be distributed across multiple smaller regions rather than requiring one large complex wiring region, thereby reducing the overall wiring region size while maintaining full scan line driving capability.
2Adaptability or versatility
If complex wiring patterns are used to connect scan driver circuits, then all scan lines can be driven, but chip size increases and assembly efficiency decreases
Solution Approach 1:
By segmenting the scan driver into multiple independent circuits with simplified wiring patterns, the chip size is reduced and wiring becomes more regular, which improves assembly efficiency and productivity while maintaining the capability to drive all scan lines.
3Adaptability or versatility
If wiring patterns include crossing wires, then comprehensive connectivity is achieved, but wiring region size increases
Solution Approach 1:
The wiring is divided into multiple independent wiring patterns, each serving a specific scan driver circuit. This eliminates the need for crossing wires within each segment, as each wiring pattern is localized and non-intersecting, thereby reducing the wiring region size while maintaining comprehensive connectivity across all circuits.
Solution Approach 2:
Multiple wiring patterns are arranged in different spatial regions or layers, effectively using dimensional separation to avoid wire crossings. Each wiring pattern operates in its own designated area, eliminating the need for complex three-dimensional routing and reducing the overall wiring region footprint.
Data Source
AI summary
An integrated circuit is provided for scan driving that can significantly reduce the chip size. In first region AODD, odd-numbered output pads OUT1, OUT3, . . . OUT173, OUT175, driver circuits DR1, DR3, . . . DR173, DR175, and flip-flops SREG1, SREG3, . . . SREG173, SREG175 in an order corresponding to the order of the odd-numbered scanning lines are each arranged as a column in the X-direction, and, at the same time, output pads OUTi, driver circuits DRi and flip-flops SREGi corresponding to the scanning lines are arranged in the same row in the Y-direction (chip width direction). In second region AEVEN, even-numbered output pads OUT2, OUT4, . . . OUT174, OUT176, driver circuits DR2, DR4, . . . DR174, DR176, and flip-flops SREG2, SREG4, . . . SREG174, SREG176 in an order corresponding to the order of the even-numbered scanning lines are each arranged as a column in the X-direction, and, at the same time, output pads OUTi, driver circuits DRi and flip-flops SREGi corresponding to the scanning lines are arranged in the same row in the Y-direction (chip width direction).