Scan Driver Leakage Circuit for Threshold Voltage Shift Compensation

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Solution Overview

Problem

Existing scan drivers in display devices, particularly those using metal-oxide thin-film transistors, face operational issues due to threshold voltage shifts, which can lead to abnormal operations and malfunctions by affecting the voltage levels of internal nodes.

Innovation Solution

The proposed scan driver incorporates a leakage circuit connected to a high gate voltage, utilizing n-type metal-oxide (NMOS) thin-film transistors with larger transistors in refresh and leakage circuits to maintain voltage levels, preventing abnormal operations even if threshold voltages shift.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If metal-oxide thin-film transistors are used in the scan driver, then the scan driver can be implemented for large-sized display devices, but threshold voltage shifts occur causing abnormal operations and malfunctions

Engineering Contradiction:
Improveapplicability to large-sized display devicesVSAvoidoperational stability against threshold voltage shifts
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary anti-action by introducing a leakage circuit that proactively compensates for threshold voltage shifts before they cause malfunction. The leakage circuit pre-establishes a current path that counteracts the voltage shift effects, preventing abnormal operations rather than reacting after failure occurs

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The leakage circuit acts as an intermediary element between the metal-oxide thin-film transistors and the overall scan driver operation. It mediates the threshold voltage shifts by providing a controlled leakage current path, isolating the main driver logic from the harmful voltage shifts

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If threshold voltage shifts are compensated using larger transistors in refresh and leakage circuits, then voltage levels are maintained preventing abnormal operations, but the device complexity and manufacturing process become more complex

Engineering Contradiction:
Improvevoltage level maintenanceVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the scan driver circuit into functional modules: input circuits, output circuits, refresh circuits, and leakage circuits. Each segment has a specific function, with the leakage circuit being a dedicated component for voltage maintenance. This modular segmentation makes the complexity manageable and the design systematic rather than monolithic

Inventive Principle:
Principle #1Segmentation

3Reliability

If threshold voltage shifts are compensated using larger transistors in refresh and leakage circuits, then voltage levels are maintained preventing abnormal operations, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvevoltage level maintenanceVSAvoidTFT manufacturing process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent utilizes parameter changes by varying the transistor sizes (channel width and length) in the leakage and refresh circuits to optimize voltage maintenance. By adjusting these physical parameters during design, the circuit achieves robust voltage level maintenance while remaining compatible with standard manufacturing processes

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10255846B2Scan driver and display device including the same
Publication Date: 2019.04.09 SAMSUNG DISPLAY CO LTD
  • US10255846B2 patent drawing
  • US10255846B2 patent drawing
  • US10255846B2 patent drawing

AI summary

A scan driver includes a plurality of stages, each outputting a scan signal in response to a scan start pulse and clock signals. Each stage includes a first input circuit applying a high gate voltage to a first node in response to the scan start pulse or the scan signal from a previous stage, a second input circuit applying a first clock signal to a second node based on the first node's voltage, a first output circuit outputting a second clock signal as the scan signal in response to the first node's voltage, a second output circuit outputting a low gate voltage as the scan signal in response to the second node's voltage, and a leakage circuit coupled to the high gate voltage and providing a current from the high gate voltage to the second node in response to the voltage of the second node having a high level.