Scan Driver Layout for Narrow-Bezel Displays With Low Parasitic Capacitance

The patent applies local quality by creating different spatial zones with different functional characteristics. The non-display area is divided into regions with different parasitic capacitance levels, allowing the scan driver to be positioned in a zone that balances both area reduction and parasitic capacitance minimization. Specifically, the scan driver is positioned adjacent to but not directly overlapping with clock lines, creating a local configuration that reduces harmful capacitance while maintaining compact overall layout.

The patent resolves the contradiction by transitioning from a two-dimensional planar arrangement to a three-dimensional stacked configuration. The scan driver and clock lines are arranged in different vertical layers rather than being purely planar, allowing them to be closer in the vertical dimension while maintaining adequate horizontal separation. This dimensional transition enables reduced non-display area without significantly increasing parasitic capacitance effects.

The patent applies segmentation by dividing the scan driver into multiple independent blocks or modules that can be distributed across different regions of the non-display area. Instead of positioning a single large scan driver that would create concentrated parasitic capacitance, the driver functionality is segmented into smaller units that can be strategically placed to minimize their collective parasitic effects while achieving compact overall layout and reduced non-display area.

The patent introduces intermediary shielding structures or grounding elements between the scan driver and clock lines. These intermediary components act as mediators that reduce parasitic capacitance coupling while allowing the scan driver to be positioned closer to clock lines for area efficiency. The shielding structures serve as intermediate layers that block or redirect parasitic electric field interactions.

The patent applies preliminary action by implementing shielding and grounding structures in advance during the layout design phase. These preliminary protective measures are built into the structure before the scan driver and clock lines are positioned adjacent to each other, preventing excessive power consumption from parasitic coupling rather than attempting to mitigate it after the fact. The shielding structures are pre-configured to block parasitic electric fields before they can cause energy loss.

The patent converts the potentially harmful close proximity of scan driver and clock lines into a benefit by using the clock line structures themselves as shielding elements. The grounded or reference-potential clock lines serve as natural shields that protect the scan driver signals from external interference while the close positioning reduces area. The previously harmful parasitic coupling is transformed into a beneficial shielding effect through proper potential configuration.