Scan Driver Layout With Overlapped Stages for Narrow-Bezel Displays
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Solution Overview
Problem
The challenge of reducing the bezel area in display devices is significant due to the spatial constraints imposed by the scan driver, which complicates the arrangement of pixels.
Innovation Solution
The implementation of a display device with overlapping first and second scan stages and non-overlapping clock signal lines, utilizing a layered structure of circuit elements and a driving power line to optimize space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the scan driver is disposed in a separate area (bezel), then the pixels can be properly arranged and driven, but the bezel area increases reducing the display area
Solution Approach 1:
The patent merges the scan driver circuit elements with the pixel array area by allowing circuit elements of different scan drivers to overlap in the same spatial region. This integration eliminates the need for a separate bezel area, as the scan driver functionality is incorporated within the display area itself, thereby reducing the overall bezel size while maintaining proper pixel arrangement and driving capability
Solution Approach 2:
The patent utilizes the vertical dimension (layer stacking) to resolve spatial conflicts. By arranging circuit elements in multiple stacked layers at different heights, the patent enables overlapping placement of circuit elements from different scan drivers in the same planar footprint. This three-dimensional arrangement allows the scan driver to occupy space within the display area without interfering with the two-dimensional pixel layout, thus reducing bezel area while maintaining manufacturing feasibility
2Productivity
If multiple scan drivers are placed adjacent to each other, then more pixels can be driven, but the required area increases the bezel size
Solution Approach 1:
The patent combines multiple scan driver circuits into a shared spatial region by allowing their circuit elements to overlap. This merging approach enables multiple scan drivers to coexist within the same area without requiring separate dedicated spaces for each driver, thus increasing the number of pixels that can be driven while preventing an increase in bezel area
Solution Approach 2:
The patent implements a nested arrangement where circuit elements of different scan drivers are placed in overlapping regions, with some circuit elements positioned in different layers within the same spatial envelope. This nesting enables multiple scan driver functionalities to be contained within a compact area, allowing more pixels to be driven without expanding the bezel dimensions
3Reliability
If clock signal lines are routed separately for each scan driver, then signal interference is avoided, but the required space increases the bezel area
Solution Approach 1:
The patent resolves the spatial conflict of routing separate clock signal lines by utilizing the vertical dimension. Clock signal lines from different scan drivers are routed at different heights (different layers) rather than requiring separate lateral paths. This three-dimensional routing approach allows multiple clock signal lines to coexist without planar interference while maintaining signal integrity, thus avoiding the need for additional bezel area to accommodate separate routing paths
Data Source
AI summary
A display device includes a first scan driver including first scan stages dependently connected to each other and a first clock signal line connected to each of the first scan stages; and a second scan driver including second scan stages dependently connected to each other and a second clock signal line connected to each of the second scan stages, wherein a first circuit element constituting the first scan stages and a second circuit element constituting the second scan stages are positioned to overlap with each other, and wherein the first clock signal line and the second clock signal line are positioned not to overlap with each other.