Scan Driver Circuit for Stable Node Voltages in Displays

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Solution Overview

Problem

Existing scan drivers face challenges in efficiently providing scan signals to pixels in display devices, particularly in managing the operation of N-type and P-type transistors, which affect the lifespan and performance of transistors due to transient bias voltages.

Innovation Solution

A scan driver design incorporating specific transistor configurations and capacitors to stabilize node voltages, including transistors with gated connections to clock and power lines, and capacitors to maintain stable turn-on levels, thereby preventing transient bias voltages and extending transistor lifespan.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional scan driver is used to provide scan signals to pixels, then the display device can operate, but transient bias voltages occur causing reduced transistor lifespan and performance

Engineering Contradiction:
Improvetransistor lifespanVSAvoidtransient bias voltages
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary action by pre-charging capacitors (first capacitor coupled to first clock line, second capacitor coupled to second clock line) before the scan signal is applied to pixels. This pre-charging ensures that when the scan signal is activated, the transistors receive stable voltages without transient bias fluctuations, thereby extending transistor lifespan and improving reliability.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If scan signals are provided to select pixels for data voltage supply, then pixel selection is achieved, but the transistor operation is affected by voltage instability

Engineering Contradiction:
Improvepixel selectionVSAvoidnode voltages
Core Design Contradiction:
Ease of operationVSStability of the object's composition

Solution Approach 1:

The patent introduces capacitors as intermediary elements between the clock lines and the transistor gates. The first capacitor is coupled between the first clock line and the first node, while the second capacitor is coupled between the second clock line and the second node. These capacitors act as mediators that stabilize the node voltages during scan signal operation, ensuring stable pixel selection without voltage composition instability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If existing transistor configurations are used in the scan driver, then the device structure is simple, but the driving characteristics of transistors are degraded

Engineering Contradiction:
Improvetransistor configurationVSAvoidtransistor driving characteristics
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies parameter changes by modifying the voltage parameters supplied to the transistor gates through the capacitor network. The capacitors maintain stable turn-on levels for the transistors by filtering voltage fluctuations, thereby improving driving characteristics without significantly increasing structural complexity. This involves changing the voltage stability parameter rather than the physical layout.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12531012B2Scan driver
Publication Date: 2026.01.20 SAMSUNG DISPLAY CO LTD
  • US12531012B2 patent drawing
  • US12531012B2 patent drawing
  • US12531012B2 patent drawing

AI summary

A scan driver includes: a first transistor having a first electrode coupled to an output scan line, a second electrode coupled to a first power line, and a gate electrode coupled to a first node; a second transistor having a first electrode coupled to a first clock line, a second electrode coupled to the output scan line, and a gate electrode coupled to a second node; a third transistor having a first electrode coupled to the first node, a second electrode coupled to a first input scan line, and a gate electrode coupled to a second clock line; and a fourth transistor having a first electrode coupled to the second node and a second electrode and a gate electrode, which are coupled to a second input scan line, wherein the first input scan line and the second input scan line are different from each other.