Overlapping Scan Driver Layout for Higher Pixel Density Displays
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Solution Overview
Problem
Existing display devices face challenges in minimizing the area occupied by transistors, leading to increased dead space and reduced pixel density, which affects the resolution and efficiency of flat panel displays.
Innovation Solution
The implementation of a scan driver design that overlaps transistors and incorporates a shielding electrode to minimize parasitic capacitance and reduce the overall area occupied by the transistors, allowing for a more compact display device with higher pixel density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are arranged in a conventional non-overlapping layout, then the transistors can be manufactured with standard processes, but the area occupied by transistors increases leading to increased dead space and reduced pixel density
Solution Approach 1:
The patent applies overlapping arrangement of transistors in the vertical dimension, where the second transistor is positioned to overlap with the first transistor. This dimensional change allows both transistors to occupy the same horizontal footprint while maintaining electrical isolation through different vertical layers, thereby reducing the overall area occupied by the transistor pair without compromising manufacturing feasibility
Solution Approach 2:
The patent implements a nested structure where the second transistor is embedded within the vertical space occupied by the first transistor. The transistors are arranged in overlapping layers with the second transistor positioned above and overlapping the first transistor, creating a nested configuration that maximizes space utilization and minimizes dead space while maintaining standard manufacturing processes
2Quantity of substance
If transistors are overlapped to reduce area, then pixel density increases, but parasitic capacitance between transistors increases affecting signal integrity
Solution Approach 1:
The patent introduces a shielding electrode as an intermediary element positioned between the first and second overlapping transistors. This shielding electrode acts as a mediator that electrically isolates the two transistors, reducing parasitic capacitance between them while allowing the transistors to maintain their overlapping arrangement for area reduction. The shielding electrode is connected to a fixed potential to provide electrostatic shielding
Solution Approach 2:
The patent applies preliminary anti-action by placing a shielding electrode between the overlapping transistors to preemptively counteract the harmful parasitic capacitance effect. The shielding electrode is positioned in advance during the manufacturing process to create an electrostatic barrier that prevents charge coupling between the transistors before signals are transmitted, thereby maintaining signal integrity despite the close proximity of overlapping transistors
Data Source
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AI summary
A scan driver includes a substrate, a first transistor on the substrate, the first transistor including a first active pattern and a first gate electrode, the first active pattern including first and second regions, and a first channel region between the first and second regions, a second transistor on the first transistor, the second transistor including a second active pattern and a second gate electrode, the second active pattern including third and fourth regions, and a second channel region between the third and fourth regions, first and second electrodes on the second transistor, the first electrode and the second electrode electrically connected to the first region and the second region, respectively, and third and fourth electrodes on the second transistor, the third electrode and the fourth electrode electrically connected to the third region and the fourth region, respectively, wherein the first and third electrodes are electrically connected.