Scan Driver Last-Stage Self-Initialization for Variable Frame Timing

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Solution Overview

Problem

Conventional scan drivers rely on an external reset signal to initialize the last stage circuit, which becomes challenging when driving frequency changes, leading to unpredictable frame period lengths and synchronization issues.

Innovation Solution

The scan driver incorporates a self-initialization signal circuit that autonomously initializes the last stage circuit using a clock signal, eliminating the need for an external reset signal and ensuring consistent operation across varying frame periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an external reset signal is used to initialize the last stage, then the initialization function is provided, but the timing controller must predict the exact moment to apply the reset signal which becomes difficult when driving frequency changes

Engineering Contradiction:
Improveinitialization timing accuracyVSAvoidtiming control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The last stage circuit performs self-initialization using its own internal clock signal without requiring external reset signals from the timing controller. The self-initialization signal circuit generates a self-init signal that triggers the initialization circuit within the same stage, making the system self-sufficient and eliminating dependency on external timing predictions.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The self-initialization signal circuit is activated in advance by the clock signal before the frame period ends. This preliminary action ensures that the last stage is initialized at the correct moment without requiring the timing controller to predict the exact end time of the frame period, thereby resolving the timing accuracy issue.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If the driving frequency changes, then the frame period length varies, but this makes it difficult to predict when to apply the reset signal

Engineering Contradiction:
Improvedriving frequency adaptabilityVSAvoidreset signal timing reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The last stage circuit uses its own internal clock signal to trigger self-initialization, making it independent of external timing predictions. This self-service mechanism automatically adapts to any driving frequency changes without affecting initialization reliability, as the circuit synchronizes with its own clock rhythm rather than relying on external timing predictions.

Inventive Principle:
Principle #25Self-service

3Reliability

If a self-initialization mechanism is implemented, then timing reliability is improved and external reset signal dependency is reduced, but additional circuit components are required

Engineering Contradiction:
Improvetiming reliabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The self-initialization signal circuit and initialization circuit are integrated within the last stage circuit itself, merging the initialization function into the existing stage structure. This consolidation minimizes additional complexity by reusing existing clock signals and circuit elements rather than adding completely separate initialization systems.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12633262B2Scan driver, display device using the same, and electronic device including the same
Publication Date: 2026.05.19 SAMSUNG DISPLAY CO LTD
  • US12633262B2 patent drawing
  • US12633262B2 patent drawing
  • US12633262B2 patent drawing

AI summary

A scan driver includes a plurality of stage circuits. A last stage circuit among the plurality of stage circuits includes a self-initialization signal unit charging a node of the last stage circuit to a first level in response to a clock signal an initialization initializing the last stage circuit when the node is at the first level.