Shared-Node Scan Driver Layout for Lower Power and Dead Space
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Solution Overview
Problem
Existing scan drivers face challenges in minimizing dead space, improving power consumption, and enhancing the reliability of transistors within the output unit.
Innovation Solution
The scan driver is designed with a configuration that includes multiple stage groups, where each stage shares an output control circuit, minimizing dead space and reducing power consumption by maintaining clock and carry clock signals at constant levels during self-scan periods, and separates transistors for improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple stage groups are used to supply scan signals to multiple scan lines, then the scan driver can cover more scan lines, but the device complexity increases
Solution Approach 1:
Multiple stage groups share common nodes (first node and second node) and power supply lines, merging the circuit structures to reduce overall complexity while maintaining the ability to drive multiple scan lines
Solution Approach 2:
The output control circuit serves multiple stages by controlling the voltage of shared nodes, making it a universal control mechanism that can manage multiple scan signal generation stages without requiring separate control circuits for each stage
2Productivity
If clock signals and carry clock signals are continuously generated, then the scan driver can maintain operation, but power consumption increases
Solution Approach 1:
The patent implements periodic action by maintaining clock signals and carry clock signals at constant levels during self-scan periods rather than continuously generating them, reducing power consumption while maintaining operational capability during display scan periods
Solution Approach 2:
The patent applies dynamics by adjusting the signal levels of clock and carry clock signals based on operational requirements - maintaining constant levels during self-scan periods and generating active signals during display scan periods, thereby optimizing power consumption
3Device complexity
If transistors are commonly connected to share nodes, then the device complexity is reduced, but the reliability of transistors decreases
Solution Approach 1:
The patent segments transistor functions by separating pull-up and pull-down transistors into distinct groups within each stage, allowing independent control and protection of each transistor type while still sharing common nodes between stages, thereby maintaining reliability without excessive complexity
Data Source
AI summary
A scan driver of the disclosure includes a plurality of stage groups configured to supply scan signals to scan lines based on clock signals, carry clock signals, and first and second powers. A first stage group of the stage groups includes a first stage configured to supply a first scan signal to a first scan line based on an input signal, a first clock signal of the clock signals, a first carry clock signal of the carry clock signals, and the first and second powers, and a second stage configured to supply a second scan signal to a second scan line based on the input signal, a second clock signal of the clock signals, a second carry clock signal of the carry clock signals, and the first and second powers. The first stage and the second stage are commonly connected to a first node and a second node.