Scan Driver Shift Registers for 3D Display Driving Modes
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Solution Overview
Problem
Existing scan drivers for large-sized display panels face challenges in efficiently driving high-definition 3D stereoscopic image displays, requiring complex circuit configurations and high clock signal counts, which complicates the implementation of simultaneous and sequential light emitting modes.
Innovation Solution
A scan driver design incorporating shift registers with input and clock signal terminals, control signal terminals, and output terminals, allowing for adjustable duty rates and overlapping signal outputs, utilizing PMOS or NMOS transistors to simplify the circuit structure and reduce clock signals, enabling flexible operation in both driving modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a complex circuit configuration is used to drive large-sized panels with high-definition 3D displays, then the display quality and 3D stereoscopic image implementation are improved, but the circuit complexity and number of clock signals increase
Solution Approach 1:
The scan driver is designed to support multiple driving modes (sequential and simultaneous light emitting modes) using the same circuit structure. The shift registers can operate in different configurations based on control signals, allowing the display to achieve high-definition 3D stereoscopic images in various modes without requiring separate circuit designs for each mode, thus improving display quality while avoiding proportional increases in circuit complexity
Solution Approach 2:
The circuit configuration dynamically adapts between sequential and simultaneous driving modes through control signals. The scan driver can switch operating modes based on display requirements, optimizing performance for different 3D stereoscopic image display scenarios while maintaining manageable circuit complexity through a single reconfigurable design rather than multiple fixed circuits
2Speed
If more clock signals are used to drive the scan driver at high speed, then the driving speed is improved, but the number of required clock signals and interface complexity increase
Solution Approach 1:
Multiple clock signal functions are merged into a unified clocking scheme. The scan driver uses a single clock signal that can drive the shift registers through phased operations, combining what would traditionally require multiple separate clock signals into one integrated timing source, thereby maintaining high driving speed while reducing interface complexity and the number of clock signal terminals required
3Reliability
If the duty rate of output signals is increased to improve pixel compensation capability, then the compensation capability is improved, but the complexity of controlling overlapping output signals increases
Solution Approach 1:
The scan driver employs periodic clock signals with specific phase relationships to control the shift registers. By using regularly timed clock cycles, the driver can generate overlapping output signals with precise duty rates that improve pixel compensation capability. The periodic nature of the operation simplifies control logic compared to arbitrary timing schemes, as the same clocking pattern repeats consistently to manage signal overlap
Data Source
AI summary
A scan driver and a display device including the same. The scan driver includes a plurality of shift registers including an input signal terminal into which an initial signal or an output signal of a previous stage is inputted, two clock signal terminals to which 2 phase clock signals are transferred, two control signal terminals to which a first control signal and a second control signal controlling a driving mode of simultaneously driving or sequentially driving output signals of all stages are transferred, and output signals terminals from which the output signals are outputted, wherein in the sequential driving mode, the first control signal and the second control signal are transferred as a predetermined first level voltage and in the simultaneous driving mode, the first control signal and the second control signal are transferred alternately as the first level voltage and a predetermined second level voltage.