Scan Driver Single Stage Mixed Transistor Signals
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Solution Overview
Problem
Conventional scan drivers for display devices with mixed transistor types, such as PMOS and NMOS, require separate stages for active-low and active-high scan signals, leading to increased size and power consumption.
Innovation Solution
A scan driver design that incorporates a single stage capable of generating both active-low and active-high scan signals using a logic circuit with specific clock signals and output buffers, reducing the need for separate stages and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate stages are used to generate active-low and active-high scan signals for mixed transistor types, then the scan driver can drive both PMOS and NMOS transistors, but the size and power consumption of the scan driver increase
Solution Approach 1:
The patent combines the functions of generating active-low scan signals (for PMOS transistors) and active-high scan signals (for NMOS transistors) into a single scan driver stage. This is achieved by using a single-stage circuit design that simultaneously produces both types of scan signals, eliminating the need for separate P-type and N-type stages. The merging of these functions reduces the overall size and power consumption while maintaining compatibility with mixed transistor types in the display panel.
2Adaptability or versatility
If separate stages are used to generate active-low and active-high scan signals, then both signal types can be produced, but the scan driver size increases
Solution Approach 1:
The patent merges the functionality of multiple stages into a single stage by designing a unified circuit that generates both active-low and active-high scan signals simultaneously. This single-stage design integrates the signal generation paths for different transistor types, reducing the physical area occupied by the scan driver while maintaining the capability to drive both PMOS and NMOS transistors.
3Use of energy by stationary object
If a single stage generates both active-low and active-high scan signals, then size and power consumption are reduced, but the circuit design becomes more complex
Solution Approach 1:
The patent implements a universal single-stage circuit design that performs multiple functions: generating both active-low and active-high scan signals, driving both PMOS and NMOS transistors, and maintaining signal integrity across different transistor types. This multi-functional design consolidates what would traditionally require separate dedicated circuits, reducing overall complexity despite the increased functionality within the single stage.
Data Source
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AI summary
A scan driver (330, 430) includes stages (100, 200, 331, 332, 431, 432), each of the stages (100, 200, 331, 332, 431, 432) receiving first and second clock signals (CLK1, CLK2) having a first low level as an active level, and a third clock signal (CLK3) having a high level as the active level. Each of the stages (100, 200, 331, 332, 431, 432) includes a logic circuit (110, 210) that changes a voltage of a first node (NQ) to the first low level based on an input signal (SIN) and the first clock signal (CLK1), and changes a voltage of the first node (NQ) to a second low level lower than the first low level based on the second clock signal (CLK2), a first output buffer (120) that outputs, as an active-low scan signal (PSS), the second clock signal (CLK2) in response to the voltage of the first node (NQ), and a second output buffer (130) that outputs, as an active-high scan signal (NSS), the third clock signal (CLK3) in response to the voltage of the first node (NQ).