Scan Driver Stage Circuit for Lower Power and Smaller Display Panels

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Solution Overview

Problem

Traditional stage circuits in scan drivers for display devices are inefficient in power usage and require significant space due to complex circuit designs.

Innovation Solution

A stage circuit design for scan drivers that includes multiple transistors and capacitors to dynamically regulate voltage levels, minimizing power consumption and reducing circuit size by connecting nodes in specific periods to enhance efficiency and compactness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If traditional stage circuit designs are used, then the circuit can perform basic voltage control functions, but power consumption increases and mounting area expands due to complex circuit designs

Engineering Contradiction:
Improvepower consumptionVSAvoidcircuit design complexity
Core Design Contradiction:
Use of energy by stationary objectVSDevice complexity

Solution Approach 1:

The patent merges multiple transistor functions into a unified stage circuit structure where transistors T1-T5 work together to achieve voltage control. Specifically, transistors T1 and T4 are connected in series between power supply VDD and ground, with their gates coupled to control node N1, while transistors T2 and T3 are connected in parallel between VDD and output node OUT, with their gates coupled to control node N2. This merged configuration reduces the number of separate control circuits needed while maintaining functional complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The stage circuit design provides multi-functionality through its ability to perform multiple voltage control operations using the same transistor structure. The circuit can operate in different modes depending on the input signals received at nodes N1 and N2, enabling it to function as both a voltage amplifier and a voltage regulator without requiring separate dedicated circuits for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If traditional stage circuit designs are used, then the circuit can perform basic voltage control functions, but mounting area increases due to complex circuit designs

Engineering Contradiction:
Improvecircuit design complexityVSAvoidmounting area
Core Design Contradiction:
Device complexityVSArea of stationary object

Solution Approach 1:

The patent merges multiple transistor functions into a unified stage circuit structure where transistors T1-T5 work together to achieve voltage control. Specifically, transistors T1 and T4 are connected in series between power supply VDD and ground, with their gates coupled to control node N1, while transistors T2 and T3 are connected in parallel between VDD and output node OUT, with their gates coupled to control node N2. This merged configuration reduces the number of separate control circuits needed while maintaining functional complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent employs capacitive coupling to connect control nodes N1 and N2, creating a temporal dimension for signal transmission. The capacitors C1 and C2 couple the output of the first inverting amplifier stage to the input of the second inverting amplifier stage, allowing signals to be transmitted through a time-delay path rather than direct physical connection, which can reduce the physical footprint of the circuit layout.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250391302A1Scan driver and display device including the same, and electronic device
Publication Date: 2025.12.25 SAMSUNG DISPLAY CO LTD
  • US20250391302A1 patent drawing
  • US20250391302A1 patent drawing
  • US20250391302A1 patent drawing

AI summary

A stage circuit controls the voltage of an output terminal based on the voltages of a first and second node. The circuit includes: a first transistor between a first input terminal and a third node, with its gate connected to a second input terminal; a second transistor between a first power input terminal and the output terminal, with its gate connected to the first node; a third transistor between a third input terminal and the output terminal, with its gate connected to the second node; a fourth transistor between the first node and the second input terminal, with its gate connected to the third node; and a fifth transistor between the first node and a second power input terminal, with its gate connected to the second input terminal. During part of the period when the first transistor is on, the third node connects to the second node.