Scan Driver Stage Design for Reduced Display Area
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Solution Overview
Problem
Current display devices have a significant non-display area, such as bezels, which limits screen size expansion without increasing the device size, and existing scan drivers are inefficient in minimizing this area while maintaining scan signal output complexity.
Innovation Solution
A scan driver design that includes stages with input circuits, signal processing circuits, and output circuits, utilizing transistors and capacitors to generate and output scan signals based on non-overlapping clock signals, allowing for reduced area occupation and efficient scan signal generation with minimal clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the number of clock signals is reduced to minimize area, then the occupied area is reduced, but the complexity of generating multiple scan signals increases
Solution Approach 1:
A single stage is designed to perform multiple functions by generating multiple scan signals (first scan signal and second scan signal) using a shared set of input circuits and signal processing circuits. The stage responds to different clock signals (first clock signal, second clock signal, third clock signal) to produce different output scan signals, allowing one stage to replace what would traditionally require multiple separate stages, thereby reducing occupied area while maintaining signal generation capability
Solution Approach 2:
The patent employs periodic clock signals with non-overlapping gate-on levels to control the generation timing of different scan signals. The first clock signal, second clock signal, and third clock signal are applied periodically with specific timing relationships, enabling the circuits to generate multiple scan signals in a sequential, periodic manner rather than requiring simultaneous complex generation, thus reducing area occupation
2Area of stationary object
If multiple scan signals are generated from a single stage, then the occupied area is reduced, but the number of transistors and capacitors required increases
Solution Approach 1:
The patent merges the functionality of multiple stages into a single stage by combining input circuits and signal processing circuits that can handle multiple clock signals. The first input terminal, second input terminal, and third input terminal feed into shared circuits that generate both the first scan signal and second scan signal. This merging reduces the total number of discrete stages and their associated support circuits, thereby reducing occupied area despite the increased component count within the single stage
Solution Approach 2:
The single stage is segmented into distinct functional blocks: input circuits that receive multiple clock signals, first signal processing circuits that generate the first scan signal, and second signal processing circuits that generate the second scan signal. This segmentation allows each block to be optimized independently while working together within the compact single-stage structure, managing the quantity of transistors and capacitors more efficiently than a monolithic design would allow
3Loss of time
If the gate-on levels of clock signals do not overlap, then scan signals can be generated at different times, but the timing control complexity increases
Solution Approach 1:
The patent uses periodic clock signals with deliberately designed non-overlapping gate-on levels to control the timing of scan signal generation. The first clock signal, second clock signal, and third clock signal are applied in a periodic sequence where their active periods do not overlap, creating a natural timing structure that simplifies control logic. This periodic timing scheme allows the circuits to generate scan signals at different times automatically based on the clock signal sequence, reducing the need for complex timing control mechanisms
Data Source
AI summary
A scan driver including a stage that includes: an input circuit controlling a voltage of a first node in response to signals at first and second input terminals; a first signal processing circuit controlling a voltage of a second node in response to the signal at the first input terminal and supplies a voltage of a first power to the second node in response to the signal at the second input terminal; a second signal processing circuit supplying a voltage of a second power to the first node in response to a signal at a third input terminal and the voltage of the second node; a first output circuit outputting the signal at the third input terminal as a first scan signal; and a second output circuit outputting a signal at a fourth input terminal as a second scan signal at a different time from the first scan signal.