Scan Driver Stage Circuit for Lower TFT Driving Voltage
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Solution Overview
Problem
Existing display devices face challenges in maintaining a constant driving voltage level for thin-film transistors in scan drivers, leading to inefficiencies and increased power consumption.
Innovation Solution
A scan driver design with altered structure and improved semiconductor layer composition for thin-film transistors connected to pull-up nodes, incorporating an output node controller and output controller to manage gate-on voltage and scan clock signals, reducing the driving voltage level and enhancing operational stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the scan driver uses conventional thin-film transistors with constant driving voltage, then the transistors can maintain stable operation, but the power consumption increases and the driving voltage level cannot be reduced
Solution Approach 1:
The patent applies dynamics by transitioning from static constant voltage operation to dynamic voltage level operation. The scan driver stages alternately operate at different voltage levels (first voltage level during active period, second voltage level during non-active period), allowing power consumption to be reduced when full driving voltage is not needed, while maintaining operational stability when required.
Solution Approach 2:
The patent implements periodic action through the alternating voltage operation of scan driver stages. Each stage periodically switches between first and second voltage levels in synchronization with the display refresh cycle, enabling reduced power consumption during non-active periods while ensuring stable operation during active display periods.
2Reliability
If the scan driver operates at high driving voltage to ensure stable transistor operation, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent uses dynamics to adjust the driving voltage level of scan driver stages based on operational requirements. During active display periods, stages operate at the first (higher) voltage level to ensure stable transistor operation. During non-active periods, stages switch to the second (lower) voltage level to reduce power consumption, thus dynamically balancing reliability and energy efficiency.
Solution Approach 2:
The patent changes the operating voltage parameter of the scan driver stages between two distinct levels. The control circuitry adjusts the voltage parameter from a first voltage level to a second voltage level based on the operational state, allowing the system to optimize the trade-off between transistor operation stability and power consumption.
3Use of energy by moving object
If the scan driver uses multiple voltage levels for different operating conditions, then power consumption is reduced, but the circuit complexity increases
Solution Approach 1:
The patent merges the voltage control functionality into the existing scan driver stage structure. The output node controller integrates the voltage level switching capability within the stage itself, combining the clock signal processing and voltage level control in a unified circuit block, thereby reducing overall system complexity despite multiple voltage levels.
Solution Approach 2:
The scan driver stage is designed with multi-functionality to handle both clock signal processing and voltage level control. The output node controller serves multiple functions: receiving clock signals, generating complementary clock signals, controlling the switching between voltage levels, and driving the scan signal lines, thereby reducing the need for separate dedicated circuits for each function.
Data Source
AI summary
The present disclosure relates to a scan driver and a display device including the same. According to an embodiment of the disclosure, a scan driver comprising stages configured to sequentially output scan signals to scan signal lines, wherein at least one stage comprises an output node controller configured to apply a gate-on voltage to a pull-up node in response to a gate control signal, and an output controller configured to output a scan signal to each of the scan signal lines, wherein the output node controller comprises a first transistor that enables the pull-up node in response to a scan clock signal, and wherein the first transistor comprises a gate electrode connected to a scan clock terminal, a first electrode connected to a previous-stage carry terminal, and a second electrode connected to the pull-up node.