Scan Driver Stress Relieving Transistors for Drain-Source Voltage
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Solution Overview
Problem
Display devices face challenges with drain-source voltage stress on transistors in scan drivers, leading to degradation due to boosted voltages during data writing and concurrent compensation periods.
Innovation Solution
Incorporating first and second stress relieving transistors between set and reset nodes to manage and lower the absolute voltage values during these periods, reducing the drain-source voltage stress on transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If voltage of set node and reset node are boosted to output scan signals, then scan signal output capability is improved, but drain-source voltage stress on transistors increases causing degradation
Solution Approach 1:
The patent introduces stress relieving transistors as intermediary elements between the set/reset nodes and the main signal path. These intermediary transistors (T10, T11) act as mediators that control and limit the voltage stress transmitted to other transistors in the circuit, allowing voltage boosting to occur while protecting critical transistors from excessive stress
Solution Approach 2:
The patent dynamically changes the operational parameters of the stress relieving transistors based on circuit conditions. The transistors are turned on during specific periods (concurrent compensation period and data writing period) when voltage boosting occurs, and turned off during other periods. This temporal parameter change allows the system to tolerate high voltage stress only when necessary for signal output, while protecting transistors during normal operation
2Reliability
If stress relieving transistors are added to reduce voltage stress, then transistor reliability is improved, but device complexity increases
Solution Approach 1:
The stress relieving transistors serve multiple functions simultaneously: they act as voltage stress limiters, signal transmission gates, and protection elements. By making these transistors multi-functional, the patent reduces the need for additional separate components, thereby limiting the increase in device complexity while achieving reliable voltage stress management
Solution Approach 2:
The patent merges the stress relief function with the existing signal transmission path by integrating stress relieving transistors into the conventional scan driver architecture. Rather than adding separate protection circuits, the stress relief capability is combined with the signal routing structure, allowing voltage stress management without significantly increasing overall device complexity
Data Source
AI summary
A scan driver includes a plurality of stages, each including a first input part configured to transfer an input signal to a first set node in response to a second clock signal, a second input part configured to transfer a first clock signal to a first reset node in response to the input signal and the second clock signal, a first output part configured to output a third clock signal as a respective scan signal in response to a voltage of a second set node, a second output part configured to output a concurrent driving signal as the respective scan signal in response to a voltage of a second reset node, a first stress relieving transistor connected between the first set node and the second set node, and a second stress relieving transistor connected between the first reset node and the second reset node.