Scan Driver Circuit for Polycrystalline TFT Reliability
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Solution Overview
Problem
Polycrystalline TFTs in panel displays experience changes in characteristics over time, leading to reliability issues and malfunction due to high on-bias voltage, affecting the driving circuit and display performance.
Innovation Solution
A scan driver design with a specific configuration of transistors and capacitors that uses a reduced number of clock signals and an output control signal to prevent voltage changes from causing malfunctions, including a first node for signal input, a second node for clock signal transfer, and transistors connected to output terminals to manage gate-on and gate-off voltages efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polycrystalline TFT is used in panel display, then manufacturing capability is improved, but reliability deteriorates due to threshold voltage changes over time under high on-bias voltage
Solution Approach 1:
The patent changes the voltage parameters applied to the TFT by using a reduced number of clock signals with lower voltage levels. Instead of applying high on-bias voltage to multiple clock signals, the invention uses fewer clock signals with optimized voltage levels, thereby reducing the stress on the TFT and preventing threshold voltage shifts while maintaining manufacturing benefits
Solution Approach 2:
The patent employs periodic clock signals with reduced frequency and duty cycle optimization. By carefully controlling the timing and periodicity of clock signals, the invention reduces the average on-bias voltage applied to the TFT, preventing characteristic degradation while maintaining adequate driving functionality
2Adaptability or versatility
If multiple clock signals are used in scan driver, then functionality is improved, but device complexity increases
Solution Approach 1:
The patent merges the functions of multiple clock signals into a reduced set of clock signals. By combining the timing control functions of several clock signals into fewer signals with optimized waveforms, the invention maintains the necessary scan driver functionality while reducing the number of clock signal lines and associated circuit complexity
Solution Approach 2:
The patent makes the remaining clock signals multi-functional by designing them to perform multiple timing control functions simultaneously. Each clock signal is engineered to serve multiple purposes in the scan driver operation, thereby reducing the total number of clock signals needed while maintaining full functionality
3Reliability
If more transistors and capacitors are added to manage voltage, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent enables the existing transistor and capacitor components to serve multiple functions through clever circuit arrangement. The same components that manage clock signal timing also inherently handle voltage stabilization and protection functions, eliminating the need for additional dedicated components and achieving reliability without increased complexity
Data Source
AI summary
A scan driver including sequentially arranged scan driving blocks, each of the blocks including a first node receiving a signal input into a driving signal input terminal based on a clock signal input into a second-clock-signal input terminal, a second node receiving a clock signal input into a first-clock-signal input terminal, a first transistor including a gate electrode connected to the second node, one electrode receiving an output control signal, and another electrode connected to an output terminal, a second transistor including a gate electrode connected to the first node, one electrode connected to a third-clock-signal input terminal, and another electrode connected to the output terminal, and a third transistor including a gate electrode connected to the third-clock-signal input terminal and one electrode connected to the first node and configured to transfer a voltage of the output terminal to the first node.