Scan Driver Circuit with Precharge for Transistor Longevity
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Solution Overview
Problem
Existing scan drivers face challenges in efficiently supplying scan signals with appropriate turn-on levels to N-type and P-type transistors, leading to potential transistor degradation and reduced lifespan due to transient bias voltages.
Innovation Solution
The implementation of scan drivers with integrated sub-scan drivers that generate scan signals with alternating polarities, utilizing P-type and N-type transistors, and incorporating capacitors to stabilize node voltages, thereby preventing transient bias voltages and improving transistor longevity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan drivers are used to supply scan signals to pixels, then the display device can operate, but transient bias voltages cause transistor degradation and reduced lifespan
Solution Approach 1:
The patent applies preliminary anti-action by introducing a preliminary scan signal before the main scan signal to pre-charge the node, preventing transient bias voltage degradation. The preliminary signal prepares the transistor gate by establishing an appropriate voltage level in advance, counteracting the harmful effect before it occurs during normal operation
Solution Approach 2:
The patent uses an intermediary circuit comprising additional transistors and capacitors that mediate between the scan driver and the pixel transistor. This intermediary structure controls the charging and discharging of the node, preventing direct exposure to harmful transient bias voltages while maintaining proper transistor operation
2Reliability
If scan signals with alternating polarities are generated using both P-type and N-type transistors, then transistor driving characteristics are enhanced, but device complexity increases
Solution Approach 1:
The patent segments the scan driver into multiple independent stages, each handling specific signal conditioning functions. By dividing the complex task of generating alternating polarity scan signals into smaller modular units with P-type and N-type transistors, the system achieves improved transistor driving characteristics while maintaining manageable complexity through functional decomposition
Solution Approach 2:
The patent implements multi-functionality by designing the scan driver circuit to simultaneously perform multiple functions: generating alternating polarity signals, controlling transistor switching, stabilizing node voltages, and preventing transient bias. This universal approach consolidates multiple functions into a unified circuit structure, improving reliability without proportionally increasing complexity
Data Source
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AI summary
A scan driver includes a first transistor (M1) having a first electrode coupled to an output scan line (GWLn), a second electrode coupled to a first power line (VGLL), and a gate electrode coupled to a first node (N1) and a second transistor (M2) having a first electrode coupled to a first clock line (NCLKL3), a second electrode coupled to the output scan line, and a gate electrode coupled to a second node (N2). Connected to the first node (N1), a third transistor (M3) has a first electrode coupled thereto, a second electrode coupled to a first input scan line (GWNL(n-2)), and a gate electrode coupled to a second clock line (PCLKL1). Connected to the second node (N2), a fourth transistor (M4) has a first electrode coupled thereto, a second electrode and a gate electrode connected together and which are coupled to a second input scan line (GWPL(n-1)). Also connected between electrodes of the fourth transistor (M4) and the second node (N2) is a further transistor (M8) having a gate connected to a control line (PENL). During low frequency driving, a low level applied to the control line prevents the second transistor (M2) from outputting signals of the first clock line (NCLKL3).