Scan Driver Circuit Voltage Difference Power Consumption

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Solution Overview

Problem

Existing scan drivers face challenges in maintaining a sufficient voltage difference between the gate and source electrodes of buffer transistors while minimizing power consumption through capacitor charge and discharge.

Innovation Solution

The proposed scan driver design includes a configuration of multiple scan stages with specific transistor and capacitor connections, utilizing power and control clock lines to manage node voltages and reduce capacitor charging/discharging, thereby enhancing voltage differences without additional external or internal elements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the voltage difference between gate and source electrodes of buffer transistor is increased to supply scan signals to all pixels, then the scan signal coverage is improved, but the power consumption increases due to capacitor charge and discharge

Engineering Contradiction:
Improvevoltage differenceVSAvoidpower consumption
Core Design Contradiction:
StrengthVSUse of energy by moving object

Solution Approach 1:

The circuit dynamically adjusts the voltage difference between gate and source electrodes based on the specific pixel row being scanned. The buffer transistor's gate voltage is controlled to provide sufficient voltage difference only when needed for scan signal output, rather than maintaining a constantly high voltage difference, thereby reducing unnecessary capacitor charge/discharge cycles and power consumption

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The circuit changes the voltage parameters of the buffer transistor dynamically during operation. By adjusting the gate voltage level according to the scanning phase and requirements, the circuit achieves adequate voltage difference for scan signal supply while minimizing excessive voltage swings that would cause unnecessary capacitor charging and discharging

Inventive Principle:
Principle #35Parameter changes

2Strength

If additional external terminals or internal elements are provided to increase voltage difference, then the voltage difference is improved, but the device complexity increases

Engineering Contradiction:
Improvevoltage differenceVSAvoiddevice complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The buffer transistor serves multiple functions: it acts as a voltage amplification element to provide the necessary voltage difference, a signal transmission element for passing scan signals to pixel rows, and a control element regulated by clock signals. By making the buffer transistor multi-functional, the circuit achieves adequate voltage difference without adding separate external terminals or internal elements

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The circuit uses its existing internal components (buffer transistor, capacitors, and clock signal lines) to generate and regulate the voltage difference. The buffer transistor self-adjusts its operation based on the clock signals it receives, eliminating the need for additional external control terminals or internal voltage regulation elements

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11217179B2Scan driver and display device including the same
Publication Date: 2022.01.04 SAMSUNG DISPLAY CO LTD
  • US11217179B2 patent drawing
  • US11217179B2 patent drawing
  • US11217179B2 patent drawing

AI summary

Provided herein is a scan driver including scan stages. A first scan stage includes a first transistor including a gate electrode coupled to a first node, a first electrode coupled to a first power clock line, and a second electrode coupled to a first scan line; a first capacitor connected between the first node and the first scan line; a second transistor including a gate electrode coupled to a second node, a first electrode coupled to the first scan line, and a second electrode coupled to a first power line; a third transistor including a gate electrode coupled to the second node, a first electrode coupled to a third node, and a second electrode coupled to a first control clock line; and a second capacitor connected between the second node and the third node.