Scan Driving Circuit Wire Layout for Lower RC Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Delays in signal transmission and voltage drops in wires within the driving circuit of display devices can affect the action of pixel circuits and image quality, leading to suboptimal performance.
Innovation Solution
The implementation of a scan driver with specific transistor configurations and wire width optimizations, where wider wires for critical clock signals reduce resistance and RC delay, thereby minimizing signal delays and voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wire width is increased to reduce resistance and RC delay, then signal transmission speed and image quality are improved, but manufacturing complexity and device area increase
Solution Approach 1:
The patent applies different wire widths to different signal paths based on their specific requirements. Critical clock signals (CLK1, CLK2) that directly affect pixel circuit operation use wider wires to reduce RC delay, while less critical signals use standard width wires. This localized optimization improves signal transmission speed where needed without unnecessarily increasing overall device complexity.
2Reliability
If wire width is increased to reduce voltage drop, then signal stability and image quality are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements selective wire width optimization where only critical clock signal paths (CLK1, CLK2) use wider wires to reduce voltage drop, while non-critical signal paths maintain standard wire dimensions. This approach improves signal stability for essential operations without uniformly increasing manufacturing precision requirements across the entire device.
3Ease of manufacture
If uniform wire width is used for all signals, then manufacturing process is simplified, but signal delay and voltage drop affect image quality
Solution Approach 1:
The patent adopts a differentiated wire width strategy where critical clock signals receive wider wires to minimize RC delay and voltage drop, while non-critical signals use standard wire widths. This selective approach maintains ease of manufacture by using standard fabrication processes for most signals while providing enhanced performance where it matters most for image quality.
Solution Approach 2:
The patent changes the wire width parameter selectively for different signal types. Clock signals that directly control pixel circuit timing use wider wires to reduce RC delay and prevent signal degradation, while data and control signals use standard wire widths. This parameter optimization improves image quality without requiring complete redesign of the manufacturing process.
Data Source
AI summary
Provided is a scan driving circuit including a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal. A width of a first wire configured to transfer the first clock signal and a width of a second wire configured to transfer the second clock signal are larger than that of a third wire configured to transfer the first signal.