Scan Driving Circuit Pull-Up Node Voltage Management
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Solution Overview
Problem
Conventional scan driving circuits in display panels experience current leakage due to high voltage at the pull-up control signal node, which reduces the reliability of the circuit, especially under prolonged operation.
Innovation Solution
A scan driving circuit with cascaded units, including a pull-up control circuit, a first reset circuit, a pull-down holding circuit, a pull-down circuit, and a pull-up circuit, which utilize specific clock signals and voltage levels to manage the electric potential of the pull-up control signal node, preventing excessive voltage and current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pull-up control signal node is charged to twice the voltage VGH using conventional reset circuits, then the circuit can operate the scan driving unit, but the thin film transistor experiences current leakage and reliability deteriorates
Solution Approach 1:
The reset function is divided into multiple independent reset circuits (first reset circuit and second reset circuit) that operate at different timing. The first reset circuit resets during the non-display period, while the second reset circuit resets during the display period, segmenting the reset operation to avoid high voltage stress on the thin film transistor during active operation.
Solution Approach 2:
The first reset circuit performs preliminary resetting of the pull-up control signal node during the non-display period before the display period begins. This preliminary action ensures the node is properly reset before high voltage signals are applied during scanning, preventing current leakage during active operation.
2Reliability
If the reset circuit receives trigger signal or reset signal, then the pull-up control signal node can be reset, but excessive voltage causes current leakage in the thin film transistor
Solution Approach 1:
The reset operation is performed periodically at specific timing intervals. The first reset circuit operates during the non-display period, and the second reset circuit operates during the display period, creating a periodic reset pattern that avoids continuous high voltage stress on the thin film transistor while maintaining proper circuit operation.
Solution Approach 2:
The patent introduces intermediate control signals (first reset signal and second reset signal) that mediate between the main clock signal and the pull-up control signal node. These intermediate signals coordinate the reset timing to ensure resetting occurs only when the thin film transistor is not subjected to high voltage, acting as a mediator to prevent voltage stress.
Data Source
AI summary
A scan driving circuit and a display panel are disclosed. A scan driving unit includes a pull-up control circuit configured for receiving a stage transmission signal of the previous two stages to charge a pull-up control signal node. A first reset circuit receives an input signal, a first clock signal and a second clock signal to reset the pull-up control signal node, wherein the input signal is a DC voltage. A pull-down holding circuit receives a low frequency clock signal and a second low frequency clock signal to hold the electric potential of the pull-up control signal node. A pull-down circuit receives a scan driving signal of the next two stages to pull down the electric potential of the pull-up control signal node. A pull-up circuit receives the first clock signal to output a stage transmission signal and a scan driving signal of the current stage.