Scan Driving Circuit Shift Register Transistor Breakdown Protection
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Solution Overview
Problem
The existing scan driving circuits for OLED displays face a risk of transistor breakdown due to high voltage drops between terminals, particularly in the shift register, which affects the stability and reliability of the display device.
Innovation Solution
A scan driving circuit with a shift register design that includes a first node control module, a second node control module, and an output control module, which manage signal levels and clock signals to prevent excessive voltage drops by controlling the levels at various nodes, thereby protecting the transistors from breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional shift register structure is used to drive OLED displays, then the circuit can operate with simple structure, but the transistor M1 is at risk of breakdown due to high voltage drop between its terminals
Solution Approach 1:
The patent segments the voltage control function by introducing an intermediate node (node N4) between the input signal path and the first node (node N1). This segmentation allows the voltage transition to occur in two stages: first at node N4, then at node N1, thereby reducing the voltage drop across transistor M1 and preventing breakdown while maintaining circuit functionality
Solution Approach 2:
The patent introduces node N4 as an intermediary element that mediates the voltage transition. Node N4 acts as a buffer that absorbs the initial voltage change from the input signal, preventing direct high voltage stress on transistor M1. This intermediary approach resolves the contradiction by protecting the transistor while preserving the signal transmission function
2Ease of operation
If the voltage level at the first node is allowed to transition freely, then the circuit operates with simple control logic, but the transistor experiences excessive voltage stress leading to breakdown
Solution Approach 1:
The patent applies preliminary action by first updating the voltage level at node N4 before updating node N1. The control unit updates node N4 in response to the input signal, and only after this preliminary update does it update node N1 based on the new node N4 level. This sequential approach prevents excessive voltage stress on transistor M1 while maintaining straightforward control logic
Solution Approach 2:
The patent implements periodic action through its multi-phase clock control mechanism. The voltage updates at different nodes occur in distinct phases controlled by clock signals, creating a periodic sequence of operations. This phased approach ensures that voltage transitions are distributed over time, reducing peak voltage stress on any single transistor while maintaining operational simplicity
Data Source
AI summary
The present disclosure provides a shift register. The shift register includes: a first node control module for controlling level at the first node; a second node control module for controlling level at a second node; and an output control module for controlling the output terminal to output high or low level. The first node control module includes an input unit configured to write the input signal into the third node and a protection unit configured to control a level at a fourth node based on a level at the third node and control writing of the level at the fourth node into the first node based on the second clock signal. The technical solution of the present disclosure can prevent the transistor for providing the third node with inputting signal from being broken down.