Scan Driving Circuit Timing Control for Display Luminance Uniformity
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Solution Overview
Problem
Display devices face challenges in achieving improved display quality due to delays in scan signal transitions, which affect luminance and contrast ratio, particularly in initializing and compensating pixels.
Innovation Solution
The implementation of a display device with a scan driving circuit that provides initialization and compensation scan signals with controlled timing, using multiple clock signals and start signals to manage the transition times of scan signals, ensuring that the delay from an inactive to an active level is optimized across different scan lines, thereby minimizing luminance differences between pixel rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the scan driving circuit provides initialization and compensation scan signals with conventional timing, then the circuit operation is simple, but luminance variations and contrast ratio deteriorate
Solution Approach 1:
The patent implements dynamic timing control for scan signals by introducing multiple clock signals (first clock signal for initialization stage, second clock signal for compensation stage) with different frequencies and phases. This dynamic timing adjustment optimizes the delay time between initialization and compensation scan signals to be less than one horizontal period, thereby reducing luminance variations and improving contrast ratio without excessive complexity
Solution Approach 2:
The patent changes the timing parameters of scan signals by controlling the delay time from inactive to active level transitions. By adjusting the frequency and phase of clock signals, the patent optimizes the timing parameters to ensure that the delay time is less than one horizontal period, which improves luminance uniformity while maintaining manageable circuit complexity
2Illumination intensity
If the delay time from initialization scan signal to compensation scan signal is long, then the pixel initialization and compensation process is complete, but luminance differences between pixel rows increase
Solution Approach 1:
The patent applies preliminary action by ensuring that the compensation scan signal is generated and transmitted quickly after the initialization scan signal. By controlling the delay time to be less than one horizontal period through optimized clock signal timing, the patent minimizes the time loss while ensuring complete pixel initialization and compensation, thereby maintaining luminance consistency across pixel rows
3Measurement precision
If multiple clock signals with different frequencies are used to control scan signal transitions, then the timing precision is improved, but the control circuit complexity increases
Solution Approach 1:
The patent segments the control function by using different clock signals for different stages: a first clock signal for the initialization stage and a second clock signal for the compensation stage. This segmentation allows precise timing control for each stage independently, achieving high timing precision while managing circuit complexity through functional division
Data Source
AI summary
A display device includes a display panel including a first pixel connected to a first initialization scan line and a first compensation scan line and a second pixel connected to a second initialization scan line and a second compensation scan line, a scan driving circuit which provides a first initialization scan signal to the first initialization scan line and the second initialization scan line in common and provides a first compensation scan signal and a second compensation scan signal to the first compensation scan line and the second compensation scan line, and a driving controller which controls the scan driving circuit. A delay time from a time point at which the first initialization scan signal transitions from an active level to an inactive level to a time point at which the first compensation scan signal transitions from the inactive level to the active level is less than one horizontal period.