Scan Driving Circuit Wiring Area Reduction
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Solution Overview
Problem
Traditional scan driving circuits for AMOLED display devices require multiple independent clock signal lines to generate scan signals, leading to increased wiring area and restricted reduction of border width, which hinders high-resolution displays.
Innovation Solution
The proposed scan driving circuit uses a signal generating unit to convert scan signals from one stage to another, allowing level changes triggered by specific scan signals, thereby reducing the number of required clock signal lines and logic elements, achieving functions typically requiring two groups of clock signal lines with only one.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple independent clock signal lines are used to generate scan signals, then scan signals of different pulse waveforms can be provided to each row of pixels, but the wiring area is greatly increased
Solution Approach 1:
The patent applies multi-functionality by enabling a single clock signal line to perform multiple functions: it generates both first scan signals and second scan signals with different pulse waveforms through a unified GOA circuit structure. The circuit uses level conversion mechanisms where the same clock signal line controls different stages to produce varied scan signals, eliminating the need for separate clock signal lines for each waveform type.
Solution Approach 2:
The patent merges previously separate clock signal line functions into a unified structure. By combining the generation of first scan signals and second scan signals under a single clock signal line control, the design consolidates multiple wiring paths into one, significantly reducing the wiring area while maintaining the ability to provide different pulse waveforms to pixel rows.
2Adaptability or versatility
If two groups of clock signal lines are used, then functions of generating multiple scan signals are achieved, but the border width is increased
Solution Approach 1:
The unified GOA circuit structure enables a single clock signal line to serve multiple purposes by generating different scan signal waveforms through internal level conversion stages. This multi-functional approach eliminates the need for separate clock signal line groups, thereby reducing the horizontal space required and minimizing the display device's border width.
Solution Approach 2:
The patent merges the functionality of two separate clock signal line groups into one unified clock signal line that controls a consolidated GOA circuit. This integration reduces the overall circuit footprint in the horizontal direction, directly contributing to a narrower border width while preserving all necessary scan signal generation capabilities.
3Adaptability or versatility
If multiple independent clock signal lines are used, then scan signals can be generated independently, but the number of logic elements is increased
Solution Approach 1:
The patent implements a unified GOA circuit where a single clock signal line controls multiple functional stages that independently generate different scan signal waveforms. This approach maintains independent scan signal generation capability through internal stage independence while sharing common control logic and clock distribution, thereby reducing the total number of logic elements compared to completely independent circuit groups.
Solution Approach 2:
The design merges separate logic element groups into a unified circuit architecture. By combining the control logic for first and second scan signal generation into a single GOA circuit structure that shares common components and clock distribution networks, the patent reduces overall logic element count while preserving the ability to independently generate different scan signal types through staged operation.
Data Source
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AI summary
A scan driving circuit, including a multi-stage shift register unit that outputs scan signals by stage under control of a clock signal (CKR, CKBR), the shift register unit includes an output terminal for outputting the scan signals, the scan driving circuit further includes a multi-stage signal generating unit, with an n-th stage signal generating unit is connected respectively to an output terminal of an n-th stage shift register unit and an output terminal of an (n+j)-th stage shift register unit, the n-th stage signal generating unit is configured to convert an outputted first level into a second level under triggering of a scan signal outputted by the n-th stage shift register unit, and convert an outputted second level into a first level under triggering of a scan signal outputted by the (n+j)-th stage shift register unit; the n and j both are positive integers. A display device including the above scan driving circuit is further provided. The above scan driving circuit and display device can reduce wiring area of clock signal lines.