Scan Dump Network Clock Domain Segmentation
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Solution Overview
Problem
Debugging hardware integrated circuits is challenging due to the opacity of many flip flops, requiring techniques to provide visibility into their workings, and existing scan dump methods are limited by high power draw and heat generation at low clock frequencies, leading to lengthy data readout times.
Innovation Solution
Implementing a scan dump network with multiple clock domains and bypasses that allow independent clocking and power gating, enabling data elements to be clocked and powered only when necessary, reducing power dissipation and allowing higher clock frequencies for faster data readout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If traditional scan dump methods are used to read data from flip flops, then debugging visibility is provided, but power draw increases and heat generation occurs at low clock frequencies
Solution Approach 1:
The scan dump network is divided into multiple clock domains, each independently controllable. This segmentation allows only the necessary clock domains to be active during data readout, reducing overall power consumption while maintaining debugging visibility.
Solution Approach 2:
The patent implements periodic clocking where clock domains are activated only during specific time intervals when data readout is required. Between these intervals, clocking is suspended to reduce power draw and heat generation, while still providing necessary debugging information.
2Loss of energy
If low clock frequencies are used in scan dump networks, then power consumption is reduced, but data readout time increases
Solution Approach 1:
The system dynamically adjusts clock frequency based on operational requirements. During active data readout phases, higher clock frequencies are used to reduce readout time. During idle phases, clocking is reduced or suspended to minimize power consumption, creating a dynamic balance between speed and energy efficiency.
Solution Approach 2:
Periodic activation of clock domains at higher frequencies during data readout intervals provides faster data retrieval, while suspending clocking between intervals reduces overall power consumption, resolving the contradiction between readout speed and energy efficiency.
3Loss of energy
If multiple clock domains with independent control are implemented, then power efficiency improves, but device complexity increases
Solution Approach 1:
The scan dump network is segmented into multiple independently controllable clock domains, allowing selective activation based on debugging needs. This segmentation improves power efficiency by activating only necessary domains, while the modular structure manages complexity through organized independence.
Solution Approach 2:
Each clock domain is designed with universal control mechanisms that can be independently activated or deactivated. This multi-functionality allows the same structural framework to serve multiple purposes: full-power operation when needed, partial operation for power savings, and coordinated operation for complex debugging scenarios, managing complexity through standardized interfaces.
Data Source
AI summary
A disclosed technique includes clock gating a plurality of data elements of a first clock domain of a scan dump network; outputting data from a plurality of data elements of a second clock domain of the scan dump network; clock gating the plurality of data elements of the second clock domain; and outputting data from the plurality of data elements of the first clock domain.