Scan Enable Signal Generation Circuit for At-Speed Testing
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Solution Overview
Problem
Existing scan test methods, such as LOC and LOS, face challenges in capturing all stages of registers at-speed and require significant area on the IC device for routing the scan enable signal, limiting their effectiveness and efficiency.
Innovation Solution
A circuit block with selector circuits and storage elements that receive clock and enable signals to generate a scan enable signal, allowing for configuration between LOC and LOS scan tests, reducing the need for global clock routing and enhancing at-speed testing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LOS scan test is used to test all stages of registers at-speed, then testing coverage is improved, but area required for routing scan enable signal as clock increases
Solution Approach 1:
The patent introduces a scan enable signal generation circuit that acts as an intermediary between the original enable signal and the scan chain. This circuit generates a derived scan enable signal that transitions at the appropriate time without requiring the original enable signal to be routed as a global clock, thus reducing routing area while maintaining LOS testing capability
Solution Approach 2:
The patent segments the scan chain into multiple groups or sets, where different groups can be tested using different scan test methods (LOC or LOS). This segmentation allows selective application of LOS testing only to groups where it is necessary, reducing the overall area required for scan enable signal routing while maintaining comprehensive testing coverage
2Reliability
If scan enable signal is routed as clock for LOS test, then all register stages can be tested at-speed, but device complexity increases
Solution Approach 1:
The patent introduces a scan enable signal generation circuit that acts as an intermediary between the original enable signal and the scan chain. This circuit generates a derived scan enable signal that transitions at the appropriate time without requiring the original enable signal to be routed as a global clock, thus reducing routing area while maintaining LOS testing capability
Solution Approach 2:
The patent makes the scan test methodology dynamic and configurable by providing control logic that can select between LOC and LOS modes. This dynamic configuration allows the system to adapt the scan enable signal generation method based on which register groups are being tested, reducing overall device complexity
3Area of stationary object
If LOC scan test is used, then device area is reduced, but testing coverage of all register stages at-speed deteriorates
Solution Approach 1:
The patent segments the scan chain into multiple groups or sets, where different groups can be tested using different scan test methods (LOC or LOS). This segmentation allows selective application of LOS testing only to groups where it is necessary, reducing the overall area required for scan enable signal routing while maintaining comprehensive testing coverage
Solution Approach 2:
The patent creates a universal scan test interface that can perform both LOC and LOS testing methods through the same hardware infrastructure. The scan enable signal generation circuit can operate in multiple modes, providing multi-functionality that achieves comprehensive testing coverage without requiring separate dedicated circuits for each test method
Data Source
AI summary
Circuits and a method for testing an integrated circuit (IC) are disclosed. A disclosed circuit block includes a selector circuit that is coupled to receive an enable signal and two clock signals. One of the two clock signals is selected as an output of the selector circuit based on the enable signal received. A storage element is coupled to receive the enable signal and the output of the selector circuit as a clock input signal. A logic gate is coupled to receive the output of the storage element and the enable signal. Another selector circuit is coupled to receive an output from the logic gate and the enable signal. The selector circuit selects either the output from the logic gate or the enable signal as a scan enable signal for a scan chain on the IC.