Scan Flip-Flop Circuit Without Transmission Gates

Solution Overview

Problem

Conventional scan flip-flops in integrated circuits require large areas and consume additional power due to the use of transmission gates for generating complementary clock signals, increasing design complexity and power consumption.

Innovation Solution

The use of complex logic gates, such as OR-AND-Inverter (OAI) and AND-OR-Inverter (AOI), eliminates the need for transmission gates, reducing power consumption and design complexity by utilizing symmetric cross-coupled logic gates and shared transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If transmission gates are used to generate complementary clock signals in scan flip-flops, then the scan chain testing function is achieved, but the area occupied increases and power consumption increases

Engineering Contradiction:

Improvescan chain testing capabilityVSAvoidflip-flop area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent removes the transmission gate component from the scan flip-flop circuit, extracting the problematic element that caused area and power issues while maintaining the scan chain testing function through alternative circuit configuration

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent combines the clock signal generation and flip-flop functionality into a more integrated structure, eliminating separate transmission gates by merging their functions into the latch circuitry itself, thereby reducing overall area

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If transmission gates are used to generate complementary clock signals in scan flip-flops, then the scan chain testing function is achieved, but power consumption increases

Engineering Contradiction:

Improvescan chain testing capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent removes the transmission gate component from the scan flip-flop circuit, extracting the problematic element that caused area and power issues while maintaining the scan chain testing function through alternative circuit configuration

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent utilizes periodic clock signaling with proper timing control to achieve scan chain testing without requiring continuous operation of transmission gates, reducing power consumption through periodic rather than continuous operation

Inventive Principle:

Principle #19Periodic action

3Reliability

If transmission gates are used in scan flip-flops, then complementary clock signals are generated, but design complexity increases

Engineering Contradiction:

Improvecomplementary clock signal generationVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the transmission gate component from the scan flip-flop circuit, extracting the problematic element that caused area and power issues while maintaining the scan chain testing function through alternative circuit configuration

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses simplified latch circuit configurations that replicate the essential functionality of transmission gate-based designs but with fewer components, effectively copying the required behavior in a more efficient manner

Inventive Principle:

Principle #26Copying

Data Source

PatentUS12431873B2Low-power flip flop circuit

Publication Date: 2025.09.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.