Scan Flip Flop Clock Gating for IC Testing Efficiency
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Solution Overview
Problem
In integrated circuit testing, insufficient pins lead to clocking conflicts among multiple circuits sharing a scan clock signal, reducing testing efficiency and increasing costs due to the need for more test patterns to resolve these conflicts.
Innovation Solution
A scan test device comprising a scan flip flop circuit and a clock gating circuit that selectively masks the scan clock signal using a predetermined bit of the test signal and a scan enable signal to generate a test clock signal, allowing flexible clocking arrangement for core circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple circuits share the same scan clock signal due to insufficient pins, then pin usage is optimized, but clocking conflicts occur that reduce testing efficiency and increase test costs
Solution Approach 1:
The patent implements dynamic clock signal control by introducing a clock gating circuit that selectively masks the scan clock signal based on test mode signals. This allows the clocking behavior to be dynamically adjusted during different phases of the testing process, enabling multiple circuits to share the same clock resource without conflicts by controlling when each circuit receives the clock signal.
Solution Approach 2:
The patent changes the control parameters of the clock signal by using test mode signals (such as capture mode vs. shift mode indicators) to control the clock gating circuit. By changing the clock signal's availability based on these control parameters, the system resolves clocking conflicts while maintaining pin sharing, thus improving testing efficiency without requiring additional pins.
2Reliability
If the number of test patterns is increased to eliminate clocking conflicts, then testing completeness is improved, but test cost increases
Solution Approach 1:
The patent introduces a clock gating circuit as an intermediary component between the shared scan clock signal and the multiple circuits under test. This intermediary selectively gates the clock signal to appropriate circuits at appropriate times, eliminating clocking conflicts without requiring an increase in the number of test patterns. This reduces test cost while maintaining testing completeness.
3Ease of manufacture
If a shared scan clock signal is used among multiple circuits, then hardware resources are optimized, but clocking conflicts reduce testing efficiency
Solution Approach 1:
The system dynamically controls clock signal distribution using test mode signals that indicate whether circuits are in capture mode or shift mode. The clock gating circuit responds to these signals to enable or disable clock transmission to specific circuits, allowing efficient time-multiplexed sharing of the clock resource without conflicts, thus maintaining fast testing speeds while optimizing hardware utilization.
Data Source
AI summary
A scan test device includes a scan flip flop circuit and a clock gating circuit. The scan flip flop circuit is configured to receive a scan input signal according to a scan clock signal, and to output the received scan input signal to be a test signal. The clock gating circuit is configured to selectively mask the scan clock signal according to a predetermined bit of the test signal and a scan enable signal, in order to generate a test clock signal for testing at least one core circuit.