Semi-Dynamic Scan Flip-Flop Circuit With Reduced D-Q Delay
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Solution Overview
Problem
Conventional semiconductor circuits with scan functions require additional hardware, leading to increased power consumption, longer signal hold times, and degraded performance due to the need for extra transistors, which complicates the integration of high-speed processing and low power consumption.
Innovation Solution
A semi-dynamic flip-flop circuit with an internal clock generator and dynamic input unit, utilizing NMOS transistors and logic gates to generate internal timing signals based on clock, scan enable, and input signals, allowing for efficient operation with a scan function while minimizing transistor count and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional hardware (transistors) is added to implement scan function, then scan testing capability is achieved, but power consumption increases and performance degrades
Solution Approach 1:
The patent merges the scan function with the standard flip-flop operation by using the same transistor network for both purposes. The scan enable signal controls whether the flip-flop operates in normal mode or scan mode, eliminating the need for separate hardware paths and reducing overall power consumption while maintaining scan testing capability.
Solution Approach 2:
The flip-flop circuit is designed to perform multiple functions using the same hardware resources. The same transistors and logic gates are used for both normal flip-flop operation and scan testing, depending on the state of the scan enable signal. This multi-functionality reduces the total transistor count and associated power consumption.
2Adaptability or versatility
If additional hardware (transistors) is added to implement scan function, then scan testing capability is achieved, but circuit area increases
Solution Approach 1:
The patent combines the scan function with the standard flip-flop structure, using the same transistor network for both operations. This merging approach eliminates redundant hardware and reduces the overall circuit area required to implement scan testing capability.
Solution Approach 2:
The circuit is designed as a universal flip-flop that can operate in either normal mode or scan mode depending on the scan enable signal. This multi-functionality allows the same hardware to serve multiple purposes, minimizing the area required while maintaining full scan testing capability.
3Adaptability or versatility
If additional hardware (transistors) is added to implement scan function, then scan testing capability is achieved, but signal hold time increases
Solution Approach 1:
By merging the scan function with the standard flip-flop operation, the patent eliminates additional signal paths that would increase hold time. The same transistor network handles both normal and scan operations, ensuring consistent and minimized signal hold time while maintaining scan capability.
4Adaptability or versatility
If additional hardware (transistors) is added to implement scan function, then scan testing capability is achieved, but output time increases
Solution Approach 1:
The patent merges scan and normal operations into a single unified circuit path, eliminating the time penalty associated with additional hardware. The same transistor network processes signals for both modes, reducing output time while maintaining full scan testing capability.
Data Source
AI summary
A flip-flop circuit having a scan function includes an internal clock generator to receive a clock signal, a scan enable signal, and a first input signal, and to output an internal timing signal based on each of the clock signal, the scan enable signal, and the first input signal. The circuit includes a dynamic input unit to receive a second input signal, the scan enable signal, a first timing signal, and the internal timing signal, and to output a first output signal. The circuit also includes a static output unit to receive the first timing signal and the first output signal and to output a static output signal, and the dynamic input unit outputs the first output signal corresponding to one of the first input signal and the second input signal, respectively, based on a status of the scan enable signal.