Scan Flip-Flop Circuit for Delay Fault Testing
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Solution Overview
Problem
Conventional testing methods for semiconductor integrated circuit devices are inadequate in detecting delay faults, which occur due to delays in signal propagation between flip-flops, and struggle to generate signal patterns necessary for effective delay fault testing.
Innovation Solution
A scan flip-flop circuit with a master-slave configuration that includes latch sections, hold sections, and output nodes, allowing for the generation and application of two signal patterns for delay fault testing by controlling the hold signal to output different signal values at consecutive time points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional low-speed test techniques are used, then open-circuit and short-circuit faults can be detected, but delay faults cannot be detected
Solution Approach 1:
The patent transitions from static low-speed testing to dynamic high-speed testing by utilizing edge-triggered flip-flops that operate synchronously with the circuit clock. The test mechanism dynamically captures signal transitions at specific timing edges, enabling detection of delay faults that occur during normal high-speed operation while maintaining compatibility with the circuit's operational dynamics.
Solution Approach 2:
The patent changes the testing parameter from steady-state logical values to transient signal transitions. By monitoring whether a signal transition propagates from one flip-flop to another within a prescribed time period, the test detects delay faults based on timing parameters rather than static logical states, thereby extending fault detection capability to speed-related defects.
2Reliability
If two-pattern signals are generated for delay fault testing, then delay faults can be detected, but test data generation becomes complex
Solution Approach 1:
The patent employs self-service by utilizing the circuit's own operational structure for testing. The same flip-flops and signal paths used during normal operation are leveraged for delay fault detection. The test mechanism automatically generates appropriate test patterns through normal circuit operation, eliminating the need for external complex test pattern generation equipment.
Solution Approach 2:
The patent achieves universality by designing a test mechanism that serves multiple functions: it monitors normal circuit operation, detects various types of faults including delay faults, and utilizes existing circuit resources. The same flip-flops serve both as functional elements and as test observation points, reducing overall system complexity.
3Productivity
If integration density and operation clock frequency are increased, then LSI performance improves, but delay faults become more prevalent
Solution Approach 1:
The patent replaces mechanical or manual testing methods with an automated electronic testing mechanism embedded within the circuit. The delay fault detection is performed electronically by comparing signal arrival times at flip-flop inputs against predetermined thresholds, substituting complex external measurement equipment with integrated electronic timing verification.
Solution Approach 2:
The patent introduces an intermediary testing mechanism that mediates between the high-speed signal transitions and the fault detection requirement. The flip-flops act as intermediaries that capture and hold signal states at specific timing points, allowing delay faults to be detected without disrupting the high-speed operation of the main circuit.
Data Source
AI summary
Disclosed is a scan flip-flop that includes a latch section, a hold section, a first output node and a second output node. The latch section holds data. The hold section captures an inner state, responsive to a control signal, to hold an output state. The first output node outputs a first output signal based on the output state. The second output node outputs a second output signal based on the inner state.