Scan Flip-Flop Circuit Fast Setup Time
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Solution Overview
Problem
Traditional scan flip-flops have slow data setup times, limiting their use in multi-gigahertz CPUs due to circuit structure and propagation delays, especially from transmission gates, which are not adequately addressed by complex control schemes and area-intensive latch structures.
Innovation Solution
A two-stage input stage with a two-gate stack and a scan and clock control logic module that eliminates the need for a transmission gate in the master latch, prioritizing the data-in path over the scan-in path, and using logically inverted clock signals to reduce propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional scan flip-flop circuit structure is used, then circuit implementation is straightforward, but data setup time is slow and propagation delay is high
Solution Approach 1:
The input stage is segmented into two separate stacks: a first stack for data input signals and a second stack for scan input signals. This segmentation allows independent optimization of each path, enabling the data input path to be optimized for speed while the scan path maintains its functionality, thereby reducing overall propagation delay and improving setup time.
Solution Approach 2:
The patent inverts the traditional approach by eliminating the transmission gate from the master latch and instead using two separate input stacks that directly drive the master latch. This inversion of the conventional architecture removes the propagation delay bottleneck associated with transmission gates while maintaining scan capability through the second stack.
2Speed
If transmission gate is used in master latch, then circuit area is reduced, but propagation delay increases and setup time worsens
Solution Approach 1:
The transmission gate is extracted and removed from the master latch structure. Instead of using a transmission gate to control data flow into the master latch, the patent uses two separate input stacks with direct connections to the master latch inputs. This extraction eliminates the propagation delay introduced by the transmission gate while maintaining area efficiency through the compact stack structure.
3Speed
If complex control schemes and area-intensive latch structures are used, then scan functionality is maintained, but timing improvement is minimal
Solution Approach 1:
The patent applies local quality by giving each input stack specialized characteristics optimized for its specific function. The first stack is optimized for data input with transistors sized and configured for maximum speed, while the second stack is configured for scan input with appropriate control signals. This localized optimization allows each path to perform its function efficiently without requiring complex global control schemes.
Data Source
AI summary
A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode.