Cross-Coupled Scan Flip-Flop Layout for Smaller DFT Cells
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Solution Overview
Problem
As semiconductor chips become increasingly integrated, existing scan testing technologies require significant time and resources, and there is a need for more efficient design for testability (DFT) methods to enhance test efficiency and chip quality standards.
Innovation Solution
A scan flip-flop with a cross-coupled structure including first and second tri-state inverters that share a common output node, allowing for efficient selection between data and scan input signals based on operation mode, and a scan test circuit incorporating these flip-flops to facilitate improved test operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional scan flip-flop structures are used, then testing functionality is achieved, but cell size and space consumption increase
Solution Approach 1:
The patent merges the data input path and scan input path into a unified structure where the same logic circuit receives inputs from both sources. The scan flip-flop integrates the multiplexer function directly into the flip-flop structure, eliminating separate control units and reducing overall cell area while maintaining both normal operation and scan testing functionality.
Solution Approach 2:
The scan flip-flop is designed to perform multiple functions: normal data input operation and scan testing operation. The same flip-flop structure can operate in either mode based on the scan enable signal, eliminating the need for separate test circuits and reducing space requirements while achieving comprehensive testing capability.
2Reliability
If complex scan testing structures are implemented, then test coverage is improved, but device complexity increases
Solution Approach 1:
The scan flip-flop employs dynamic switching between normal operation mode and scan testing mode through the scan enable signal. The multiplexer dynamically selects between data input and scan input based on the operation mode, allowing the same hardware structure to adapt to different functional requirements without increasing complexity.
Solution Approach 2:
The unified scan flip-flop structure serves dual purposes: normal circuit operation and scan testing. By integrating both functions into a single structure with mode switching, the patent achieves comprehensive test coverage without requiring separate complex test circuits, thereby maintaining device simplicity.
3Reliability
If separate test circuits are added, then testing capability is enhanced, but space efficiency decreases
Solution Approach 1:
The patent combines the scan testing functionality directly into the existing flip-flop structure rather than adding separate test circuits. The multiplexer is integrated within the flip-flop, sharing the same physical space and resources, which enhances testing capability while maintaining high space efficiency in the semiconductor chip.
Data Source
AI summary
A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.