Analysis Program Identifies Scan Flip-Flop Modification Locations
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Solution Overview
Problem
In the scan shift approach for delay testing in semiconductor integrated circuit design, underkill issues arise due to the difficulty in identifying where modifications are needed to avoid redundant faults, which can lead to incomplete testing.
Innovation Solution
An analysis program and device that reads circuit data, generates test data for delay faults, analyzes for redundant faults, and presents modification locations to avoid underkill by identifying cause locations within the scan flip-flops and gate circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automatic test pattern generation is used for delay testing, then test data generation efficiency is improved, but identification of underkill causes and modification locations becomes more difficult
Solution Approach 1:
The system performs feedback analysis by automatically detecting redundant faults generated during test pattern generation and tracing back to identify the causes (underkill conditions) and their locations in the circuit. This feedback mechanism enables the system to automatically resolve the contradiction by using the efficiency of automated test generation while adding an analysis layer that identifies underkill causes without manual intervention.
Solution Approach 2:
The analysis device acts as an intermediary between the automatic test pattern generator and the circuit design. It receives test data and circuit information, analyzes for redundant faults, identifies underkill causes, and presents modification locations. This intermediary function allows the system to maintain high productivity from automated generation while adding the detection and measurement capabilities needed to identify underkill issues.
2Reliability
If scan shift approach is used for delay testing, then testing capability is improved, but underkill issues arise due to redundant faults
Solution Approach 1:
The system converts the harmful redundant faults that cause underkill into useful diagnostic information. By analyzing the redundant faults generated during scan shift testing, the system identifies the underlying underkill causes and presents modification locations. This transforms the harmful effect of redundant faults into a beneficial analysis capability that improves testing reliability by preventing underkill conditions.
Solution Approach 2:
The analysis device provides feedback on redundant faults generated during scan shift testing. It automatically detects when redundant faults occur, traces them back to their causes in the circuit, and presents modification locations. This feedback mechanism allows the system to maintain the reliability benefits of scan shift testing while automatically identifying and addressing underkill issues.
3Reliability
If circuit modifications are made to avoid underkill, then testing completeness is improved, but complexity of determining modification locations increases
Solution Approach 1:
The analysis device performs self-service by automatically analyzing circuit data, detecting redundant faults, identifying underkill causes, and determining modification locations without requiring manual intervention. The system uses its own computational resources to process circuit information and generate analysis results, thereby improving testing completeness while avoiding the complexity burden that would otherwise require manual analysis.
Solution Approach 2:
The system replaces manual analysis methods with automated computational analysis. Instead of requiring human experts to manually trace and identify underkill causes and modification locations, the system uses computer-based algorithms to automatically process circuit data, detect redundant faults, and present analysis results. This substitution dramatically reduces the complexity burden while improving testing completeness.
Data Source
AI summary
A non-transitory computer-readable recording medium stores an analysis program for causing a computer to execute a process including: reading circuit data; trying to generate test data for a delay fault to be targeted; analyzing whether an underkill is caused when the targeted delay fault results in a redundant fault; and presenting circuit modification locations to avoid the underkill, based on an analysis result, when the underkill is caused.


