Scan Flip-Flop Multiplexer Delay Extension
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing scan flip-flops face hold-time violations due to differences in signal delays between normal operation and scan test modes, leading to increased design complexity, resource consumption, and potential failures in meeting timing specifications, especially in advanced fabrication processes.
Innovation Solution
A scan flip-flop design incorporating a multiplexer formed by multiple stacked transistors (Mp and Mn) that increases delay time along the scan chain while maintaining normal operation timing, allowing for effective hold-time management and reduced buffer usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional buffer circuits are inserted along the scan chain to address hold-time violations, then the timing specification is met, but the area overhead, power consumption, and design complexity increase
Solution Approach 1:
The patent merges the buffer function with the existing scan flip-flop structure by adding a third transistor to the multiplexer. This integration eliminates the need for separate buffer circuits while achieving the same delay extension effect, thereby reducing area overhead and design complexity while still meeting timing specifications
Solution Approach 2:
The modified multiplexer structure serves multiple functions: it maintains the data selection capability between normal operation mode and scan test mode, while simultaneously providing the additional delay function that previously required separate buffer circuits. This multi-functionality reduces the overall device complexity
2Reliability
If additional buffer circuits are inserted along the scan chain to address hold-time violations, then the timing specification is met, but the power consumption increases
Solution Approach 1:
By merging the buffer function into the existing multiplexer structure of the scan flip-flop, the patent eliminates the need for separate buffer circuits that would consume additional power. The same delay extension is achieved using the existing transistor network, thereby reducing overall power consumption while meeting timing specifications
3Reliability
If the scan chain delay is increased to meet hold-time requirements, then the timing specification is met, but the area overhead increases
Solution Approach 1:
The patent applies local quality by adding functionality to a specific location within the existing scan flip-flop structure rather than adding separate components. The third transistor is strategically placed in the multiplexer to provide the necessary delay extension, achieving hold-time compliance with minimal area overhead by utilizing the existing layout space efficiently
Data Source
AI summary
Scan flip-flop and associated method are provided. The scan flip-flop includes a data input terminal, a scan input terminal, a flip-flop circuit, a first transistor and a plurality of second transistors. A gate of the first transistor is coupled to the scan input terminal, gates of the second transistors are commonly coupled to an enabling signal, drains and sources of the first transistor and the second transistors are serially coupled to the flip-flop circuit, so as to increase a delay between the scan input terminal and the flip-flop circuit.