Scan Flip-Flop Circuit Reducing Area and Power via Segmented Latches
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Solution Overview
Problem
Existing scan flip-flop designs either increase circuit area significantly or impact functional path performance, with known techniques either requiring additional latches and clock signals or increasing power consumption.
Innovation Solution
A two-latch flip-flop design controlled by two non-overlapping clock signals and a control signal, which isolates inputs based on the scan enable signal, allowing scan operation without additional latches and with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a multiplexed flip-flop with multiplexer is used for scan testing, then scan capability is achieved with small area increase, but functional path performance is degraded
Solution Approach 1:
The flip-flop is segmented into two separate latches (master latch and slave latch) that operate independently in different modes. The master latch handles functional mode operations while the slave latch handles scan mode operations, allowing each latch to be optimized for its specific function without the performance degradation caused by multiplexers in the functional path.
Solution Approach 2:
The circuit dynamically switches between functional mode and scan mode by controlling which latch is active and which input path is enabled. The scan enable signal dynamically controls the tristate devices to isolate either the data input or scan input, allowing the circuit to adapt its behavior based on operational requirements without permanent structural changes.
2Speed
If clocked scan flip-flops with additional latch are used, then functional path performance is maintained, but circuit area increases by 30-50%
Solution Approach 1:
The master latch serves dual purposes: it functions as the primary data capture element in functional mode and as the input stage for scan operations in scan mode. This multi-functionality eliminates the need for a completely separate scan latch, reducing the area increase to only 5-10% while maintaining functional performance.
Solution Approach 2:
The functional data path and scan data path are merged through the common master latch structure. The same master latch that captures functional data also receives scan data when in scan mode, consolidating the data capture functionality into a single shared element rather than requiring separate latches for each mode.
3Adaptability or versatility
If multiple control signals are added to achieve correct functionality, then scan operation is enabled, but device complexity increases
Solution Approach 1:
The circuit uses periodic non-overlapping clock signals (functional clock and scan clock) to control latch operations. These periodic clock signals automatically enable the correct latch at the appropriate times without requiring complex combinational logic, reducing control complexity while maintaining full scan functionality.
Solution Approach 2:
The scan enable signal acts as an intermediary that controls the tristate devices to isolate the appropriate input path. This single control signal mediates between the data input and scan input, selecting which path is active without requiring multiple complex control signals for each isolation decision.
Data Source
AI summary
The application discloses a circuit comprising at least one flip flop, said flip flop comprising: a master latch and a slave latch; a data signal input and a scan signal input arranged in parallel to each other and each input comprising a tristateable device; and a scan enable signal input, a functional clock signal input and a scan clock signal input; wherein: in response to a first predetermined value of said scan enable signal indicating a functional mode of operation, said scan input tristateable device is operable to isolate said scan input from said master latch, and said master latch is operable in response to said functional clock to receive data from said data input and to output data to said slave latch and said slave latch is operable in response to said functional clock to receive data from said master latch and to output data at said data output; and in response to a second predetermined value of said scan enable signal indicating a scan mode of operation said data input tristateable device is operable to isolate said data input from said master latch, and said master latch is operable in response to said scan clock to receive data from said scan input and said slave latch is operable in response to said functional clock to receive data from said master latch and to output data at said scan output.