Scan Flip-Flop Buffer Gating for Hold-Time Compliance
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Solution Overview
Problem
Scan flip-flop circuits in scan chains face hold-time violations due to PVT variations and clock skew, leading to the need for additional buffers that occupy circuit space and consume unnecessary power, especially in normal operating modes.
Innovation Solution
A flip-flop circuit design that includes a buffer and a scan flip-flop, where the buffer generates a buffering signal based on a test signal and a data signal, and the scan flip-flop generates a test-enable reverse signal to control the buffering signal, allowing for reduced buffer count to achieve desired delay times without increasing power consumption in normal modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional buffers are added to the scan path to fix hold-time violation, then the hold-time violation is resolved, but the circuit area occupied increases and power consumption increases
Solution Approach 1:
The buffer is designed with dynamic power gating control using the test-enable signal. The buffer operates only during test mode when the test-enable signal is active, and is powered down during normal operation. This dynamic control allows the buffer to provide necessary delay for hold-time compliance during testing while consuming minimal area and power during normal operation.
Solution Approach 2:
The buffer's power state is changed based on the test-enable signal parameter. When test-enable is high, the buffer is powered on to provide the required delay; when test-enable is low, the buffer is powered off. This parameter-based control resolves the contradiction by making the buffer's area and power consumption conditional rather than constant.
2Reliability
If additional buffers are added to the scan path to fix hold-time violation, then the hold-time violation is resolved, but the power consumption increases
Solution Approach 1:
The buffer incorporates dynamic power gating controlled by the test-enable signal. During test mode, the buffer is activated to provide necessary signal delay for hold-time compliance. During normal operation, the buffer is deactivated through power gating, eliminating unnecessary power consumption while maintaining the ability to provide delay when needed for testing.
Solution Approach 2:
The power consumption parameter of the buffer is dynamically changed based on the test-enable signal. The buffer transitions between high-power (active during test) and low-power (inactive during normal operation) states, resolving the contradiction between needing delay for reliability and minimizing power consumption.
3Reliability
If the buffer operates continuously to provide delay, then the hold-time violation is fixed, but unnecessary power is consumed during normal mode
Solution Approach 1:
The buffer's operation is made dynamic through test-enable controlled power gating. The buffer provides delay continuously only when needed during test mode, and remains in a low-power state during normal operation. This dynamic operation eliminates unnecessary energy loss while maintaining hold-time compliance during testing.
Solution Approach 2:
The operational state parameter of the buffer is changed based on test-enable signal. The buffer transitions from continuous operation (high energy consumption) to gated operation (low energy consumption) depending on whether testing is in progress, resolving the contradiction between maintaining delay and reducing energy loss.
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
A flip-flop circuit is provided. The flip-flop circuit receives a test signal at a test-in terminal and a data signal at a data-in terminal and generates a scan-out signal. The flip-flop circuit includes a buffer and a scan flip-flop. The buffer has an input terminal coupled to the test-in terminal and an output terminal and further has a first power terminal and a second power terminal. The buffer operates to generate a buffering signal. The scan flip-flop receives the buffering signal and the data signal. The scan flip-flop is controlled by a test-enable signal to generate the scan-out signal according to the buffering signal or the data signal. The scan flip-flop further generates a test-enable reverse signal which is the reverse of the test-enable signal. The first power terminal of the buffer receives the test-enable signal or the test-enable reverse signal.