Scan-Enable D Flip-Flop Clock Gating for Lower Set-Up Time
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Solution Overview
Problem
Scan/scan enable D flip-flops in integrated circuits experience latency delays due to circuit interpositions on data signal paths, leading to larger-than-necessary set-up times, which complicates chip design and degrades performance.
Innovation Solution
Incorporating a selection logic circuit in the clock path and a pass structure in the data path to selectively enable or disable clock signals, allowing for reduced set-up times by controlling the passage of data signals based on enabled clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multiplexer circuit is present in the data path to selectively output data signal, feedback signal, or scan input signal, then the flip-flop can perform multiple functions (normal operation and scan testing), but the set-up time increases due to latency delay
Solution Approach 1:
The patent introduces a clock signal as an intermediary control mechanism. Instead of using a multiplexer in the data path, the invention uses clock signal gating to selectively enable or disable data path transmission based on operational mode (normal vs. scan). This mediator approach eliminates the need for complex data path switching while maintaining multi-functionality.
Solution Approach 2:
The patent inverts the conventional approach by placing selection logic in the clock path rather than the data path. Instead of switching data signals through a multiplexer, the invention switches clock signals to control when data can pass through the flip-flop. This inversion transfers the selection function from data domain to clock domain, reducing data path latency.
2Adaptability or versatility
If a multiplexer is used for signal selection in the data path, then the flip-flop can selectively input data signal, feedback signal, or scan input signal, but the circuit complexity increases
Solution Approach 1:
The clock signal serves as a mediator that controls the operational mode without requiring complex data path switching circuits. By using clock gating mechanisms, the patent achieves signal selection functionality with simpler logic compared to a full multiplexer implementation in the data path.
Solution Approach 2:
The patent moves the selection logic from the data path to the clock path. This inversion replaces complex data path multiplexing with simpler clock signal control, thereby reducing overall circuit complexity while maintaining the ability to selectively input different signals based on operational mode.
3Adaptability or versatility
If selection logic circuit is placed in the data path, then signal selection can be achieved, but latency delay increases and performance degrades
Solution Approach 1:
The patent inverts the placement of selection logic from data path to clock path. This fundamental repositioning allows signal selection to occur through clock gating rather than data path multiplexing, thereby eliminating the latency delay that would otherwise be introduced by selection logic in the critical data path.
Solution Approach 2:
The clock signal acts as an intermediary that enables or disables data transmission based on operational mode. This approach achieves signal selection functionality without introducing latency into the data path, as the selection occurs in the clock domain rather than the data domain, thereby maintaining flip-flop performance.
Data Source
AI summary
In accordance with an embodiment, an integrated circuit comprises a master-slave flip-flop, a selection logic circuit, and a pass structure. The selection logic circuit is configured to selectively enable or disable one or more clock signals. The pass structure is configured to pass a data signal to the master-slave flip-flop in response to a selected clock signal being enabled.