Scan Flip-Flop Latch Control for At-Speed Delay Testing
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Solution Overview
Problem
Existing scan test circuits using LSSD type flip-flops face challenges in performing transition delay failure tests between Pos-type and Neg-type flip-flops when connected, due to the inability to input necessary scan shift clock signals with opposite polarities, and require inverters which hinder actual operating frequency delay failure testing.
Innovation Solution
A scan flip-flop circuit with a master latch and a slave latch, where one is a high-level latch and the other a low-level latch, allowing for different clock signals to control each latch, enabling accurate shift operations and delay testing at actual operating frequencies without the need for inverters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LSSD type flip-flops are used in scan test circuits, then scan shift operations can be performed, but transition delay failure tests between Pos-type and Neg-type flip-flops cannot be accurately conducted due to inability to input clock signals with opposite polarities
Solution Approach 1:
The flip-flop is divided into two independent latch circuits: a master latch and a slave latch. Each latch can be controlled by different clock signals, allowing the master latch to receive a first clock signal and the slave latch to receive a second clock signal with opposite polarities. This segmentation enables accurate transition delay failure testing between Pos-type and Neg-type flip-flops while maintaining scan shift functionality.
2Reliability
If inverters are added to generate clock signals with opposite polarities, then transition delay testing becomes possible, but the circuit complexity increases and actual operating frequency delay testing is hindered
Solution Approach 1:
Each latch circuit is designed to universally accept different clock signal polarities. The master latch can be configured to operate with rising or falling edge triggered clock signals, and the same applies to the slave latch. This multi-functionality eliminates the need for inverters to generate opposite polarity clock signals, reducing circuit complexity while enabling transition delay testing between Pos-type and Neg-type flip-flops.
3Measurement precision
If two independent clock signals are input to master and slave latches, then accurate shift operations are enabled, but the device complexity increases
Solution Approach 1:
The clock signal control is made dynamic and configurable. Control signals can selectively enable or disable the first and second clock signals based on the desired operation mode. During scan shift operations, both clock signals are enabled for accurate timing control. During transition delay testing, the clock signals can be configured with opposite polarities. This dynamic control reduces unnecessary complexity while maintaining measurement precision.
Data Source
AI summary
Provided is a flip-flop circuit which a small-sized test circuit with hold free and can perform test in an actual operating frequency. A Pos-type F/F includes a master latch (Low level latch) that selectively receives data or scan test data in synchronization with a rising edge of a clock signal, and a slave latch (High level latch) that receives the data from the master latch. In a scan shift operation, the master latch captures scan data signal input SIN in a Low period of a scan shift clock signal SCLK1 and outputs the data to the slave latch. The slave latch captures the output of the master latch in a High period of a scan shift clock signal SCLK2 having a different edge position from the SCLK1 and outputs the data to Q.