Scan Flip-Flop Preset Logic for Fault Isolation in Scan Chains
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Solution Overview
Problem
Existing semiconductor chip testing methods fail to accurately identify malfunctioning scan flip-flops within scan chains, leading to inaccurate design for testing (DFT) results due to corrupted scan data from faulty flip-flops.
Innovation Solution
Implementing a pre-setting combinational logic circuit within scan chains to preset each flip-flop to a specific known value, allowing identification of malfunctioning flip-flops by comparing actual output to the expected value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional scan chain testing is used, then the testing process is simple, but malfunctioning flip-flops cannot be accurately identified due to corrupted data propagation
Solution Approach 1:
The patent applies preliminary action by pre-setting known values into the scan flip-flops before the actual testing process. The pre-setting circuit injects predetermined test patterns (such as all-ones or all-zeros) into the scan chain, establishing a known reference state that enables accurate identification of malfunctioning flip-flops during subsequent testing operations.
Solution Approach 2:
The patent introduces an intermediary pre-setting circuit that acts as a mediator between the test controller and the scan flip-flops. This circuit includes preset control logic and data injection mechanisms that facilitate the insertion of known test patterns, serving as an intermediate layer that enables precise fault detection without directly modifying the core scan chain structure.
2Reliability
If pre-setting combinational logic circuit is implemented, then accurate identification of malfunctioning flip-flops is enabled, but the device complexity increases
Solution Approach 1:
The patent merges the pre-setting functionality with the existing scan chain structure by integrating preset control logic into the scan enable mechanism. The pre-setting circuit shares control signals and data paths with the normal scan operation, combining multiple functions (presetting and scanning) into a unified circuit architecture that reduces overall complexity.
Solution Approach 2:
The scan chain circuit is designed with multi-functionality to perform both normal scanning operations and pre-setting operations using the same hardware resources. The preset control logic can be selectively activated based on test mode signals, allowing the circuit to serve multiple purposes (fault detection and normal operation) without requiring separate dedicated circuits for each function.
Data Source
AI summary
Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.