Scan Flip-Flop Latch Topology With Fewer Inversions
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Solution Overview
Problem
Flip-flop circuits face challenges in achieving faster operation, reduced power consumption, and smaller footprint due to signal inversions and the need for additional components like scan multiplexers and transmission gates.
Innovation Solution
The flip-flop circuit design reduces signal inversions by merging or replacing the scan multiplexer, utilizing cross-coupled Or-And-Inverter (OAI) and And-Or-Inverter (AOI) logic gates, and eliminating the need for a conventional multiplexer, thereby reducing transistor count and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional flip-flop circuits use scan multiplexers and transmission gates, then data input functionality is achieved, but circuit area and complexity increase
Solution Approach 1:
The patent merges the scan multiplexer functionality directly into the master latch circuit by using the same transmission gates and control signals for both data input and scan input modes. This integration eliminates the need for separate multiplexer components, thereby reducing circuit area while maintaining full data input functionality through the shared gate structure.
Solution Approach 2:
The transmission gates in the master latch are designed to serve multiple functions: they act as data input switches during normal operation and as scan input switches during testing mode. This multi-functionality is achieved by controlling the same gates with different signal combinations, eliminating the need for dedicated scan multiplexer components and reducing overall circuit complexity.
2Adaptability or versatility
If conventional flip-flop circuits include multiple transmission gates and multiplexers, then complete functionality is achieved, but transistor count increases
Solution Approach 1:
The patent combines the transistor structures of the scan multiplexer and data input paths into a unified transmission gate configuration. By sharing transistor resources between scan and data paths and using common control logic, the design achieves complete functionality with a reduced transistor count compared to conventional separate implementations.
Solution Approach 2:
The transmission gates are designed to perform multiple functions using the same transistor structures. The gates can switch between data input mode and scan input mode by changing control signals, eliminating the need for separate transistor sets for each function and thereby reducing the total transistor count while maintaining complete functionality.
3Reliability
If conventional flip-flop circuits use traditional logic gate configurations, then reliable operation is achieved, but power consumption increases
Solution Approach 1:
The patent extracts and eliminates redundant logic gates from the conventional flip-flop configuration. By removing unnecessary inversion stages and simplifying the logic path while maintaining the essential latch functionality, the design achieves reliable operation with reduced switching activity and lower power consumption.
Solution Approach 2:
The patent changes the logic gate configuration parameters by using alternative logic structures that achieve the same functionality with fewer transitions. This optimization reduces the switching frequency and number of active gates, thereby maintaining reliability while decreasing power consumption through parameter optimization of the logic circuit.
Data Source
AI summary
A flip flop circuit includes a first master portion, a second master portion, at least one determining portion and a slave portion. The first master portion is configured to operate at a first mode and to receive a first input and generate first master outputs. The second master portion is configured to operate at a second mode and to receive a second input and generate second master outputs. The at least one determining portion is configured to receive at least one enable signal, and has determining inputs and determining outputs. The determining inputs are connected to the first master outputs and the second master outputs. The determining portion is configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal. The slave portion is configured to receive the determining outputs and generate an output signal.