Scan Flip-Flop Timing Control to Prevent Clock-Skew Race Conditions
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Solution Overview
Problem
Integrated circuit designers face challenges in preventing race conditions due to timing differences between clock signals, which can cause setup or hold violations and corrupt scan data, especially when using limited resources like dedicated test pins and silicon footprint for complex tests.
Innovation Solution
A system and method that utilize a control signal, such as the scan enable signal, to prevent race conditions by ensuring that the slave latch of one flip flop and the master latch of another are not concurrently open, by timing the change in the control signal to align with the cycle of the second clock signal, reducing overhead and resource consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scan mode is used to test integrated circuits, then testing capability is improved, but race conditions occur due to clock skew between different clock signals
Solution Approach 1:
The patent applies preliminary action by asserting the scan enable signal before the clock signal transitions. This timing arrangement ensures that the transfer gates are already in the correct state to prevent race conditions, allowing scan mode testing to proceed reliably without data corruption from clock skew between different clock domains
2Adaptability or versatility
If timing differences between clock signals are allowed, then operational flexibility is improved, but setup or hold violations occur causing scan data corruption
Solution Approach 1:
The patent applies dynamics by making the transfer gates controllable through the scan enable signal. This dynamic control allows the system to adapt to different timing conditions between clock signals, preventing setup and hold violations while maintaining operational flexibility across different scan chain configurations and clock skew scenarios
3Productivity
If scan logic circuits are connected in serial manner to form long scan chains, then testing coverage is improved, but resource consumption increases
Solution Approach 1:
The patent applies universality by designing scan logic circuits that can operate in multiple modes (scan mode and functional mode) with a unified structure. The same flip-flop infrastructure serves both testing and operational functions, allowing long scan chains to achieve comprehensive testing coverage without proportionally increasing overall device complexity
Data Source
AI summary
A system that includes a first flip flop that is serially coupled to a second flip flop. The first flip flop includes a transfer circuit that is coupled between a master latch and a slave latch. The master latch of the first flip flop latches a scan data signal during a first portion of a cycle of a first clock signal that is provided to the first flip flop. The transfer circuit is conductive during a sub-portion of a second portion of the cycle of the first clock signal. The sub-portion starts after an occurrence of a predefined change in a control signal provided to the slave latch. The predefined change occurs after an estimated start of a first portion of a cycle of a second clock signal that is provided to the second flip flop. A master latch of the second flip flop latches the scan data signal during a first portion of a next cycle of the second clock signal.