Multi-mode Programmable Scan Flop Circuit Design
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Solution Overview
Problem
Existing scan testing methods for integrated circuits lack flexibility in operational modes, requiring external multiplexers for bypassing scan elements and limiting the ability to selectively apply test stimulus data and capture test results without disrupting normal circuit operations.
Innovation Solution
A scannable flop circuit with a latch circuit that allows operation in multiple modes, including Full Scan, No Scan, Scan Load Only, Scan Observe Only, Scan Shift Protect, Scan Flush Reset, Scan Toggle Reset, and Scan Flush/Toggle Reset, enabling selective data flow and feedback paths without external multiplexers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external multiplexers are used for bypassing scan elements, then scan testing flexibility is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the multiplexer functionality directly into the scan element by integrating a latch circuit that can be configured in different modes (full scan, no scan, scan load only, scan observe only). This integration eliminates the need for separate external multiplexers while providing the same bypassing and testing flexibility, thereby reducing overall device complexity and cost.
Solution Approach 2:
The scan element is designed with multi-functionality through the latch circuit that can operate in multiple modes depending on control signals. The same scan element can serve as a bypass element, a test element, or a normal circuit element, eliminating the need for separate dedicated components and reducing device complexity.
2Reliability
If scan elements are configured for full scan operation, then testing capability is improved, but normal circuit operation is disrupted
Solution Approach 1:
The patent implements dynamic reconfiguration of the scan element through control signals that can switch between different operational modes. The latch circuit can be dynamically changed from full scan mode to no scan mode or other intermediate modes, allowing the circuit to adapt its behavior based on whether testing or normal operation is required, thus maintaining both testing capability and normal circuit operation without disruption.
Solution Approach 2:
The patent applies local quality by enabling selective scanning of individual scan elements within a scan chain. Through the latch circuit configuration, specific elements can be put in bypass mode while others remain in test mode, allowing localized testing without affecting the entire circuit's normal operation, thus balancing testing capability with operational continuity.
Data Source
AI summary
A scannable flop circuit configured for operation in a multiple modes. The scannable flop circuit includes a functional flop having a data input, a clock input, and a data output, a scan flop having a scan data input and a scan data output, and a latch circuit coupled between the functional flop and the scan flop. The latch circuit includes one or more mode signal inputs to enable selection of an operating mode. In a first mode, the latch circuit is configured to enable the functional flop to provide a data signal to the scan flop. In a second mode, the latch circuit is configured to enable the scan flop to provide a data signal to the functional flop. In a third mode, the latch circuit is configured to provide a feedback path in order to feed back to the functional flop a signal generated by the functional flop.