Scan Flop Fault Localization via Modified Test Patterns
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Solution Overview
Problem
Current methods for testing integrated circuits using automated test equipment struggle to accurately localize scan flops associated with faults due to compression of output data, which can lead to ambiguity in identifying the specific scan flop causing unexpected outputs.
Innovation Solution
Generating a series of test patterns with varying control data to isolate the scan flop responsible for faults by identifying common fault-generating scan flops across different test patterns, allowing for precise localization of the faulty component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If output of scan flops is compressed into a bit stream to reduce data bandwidth and pins, then data bandwidth and pin count are reduced, but information extraction capability deteriorates
Solution Approach 1:
The patent segments the fault diagnosis process into multiple stages by generating multiple test patterns with different control data. Each test pattern targets specific scan flops, allowing the system to identify faulty flops through iterative elimination rather than requiring all scan flop outputs to be simultaneously observable in a single compressed bit stream.
Solution Approach 2:
The patent employs periodic action by generating a series of test patterns in sequence, where each test pattern uses different control data to activate different subsets of scan flops. This periodic testing approach allows fault localization over time without requiring full parallel observation of all scan flop outputs.
2Quantity of substance
If multiple scan flops outputs are compressed into a bit stream, then data bandwidth is reduced, but fault localization precision deteriorates
Solution Approach 1:
The patent divides the set of scan flops into smaller subsets by using different control data in different test patterns. Each test pattern activates a specific subset of scan flops, and by comparing results across multiple patterns, the faulty flop is identified through process of elimination rather than requiring precise identification from a single compressed output stream.
Solution Approach 2:
The patent changes the control data parameter across multiple test patterns to selectively activate different scan flops. By varying this control parameter, the system can isolate individual scan flops for testing without requiring them all to be simultaneously observable, thereby maintaining fault localization precision while using compressed bit stream output.
3Loss of time
If a single test pattern is used for fault detection, then testing time is reduced, but fault localization capability deteriorates
Solution Approach 1:
The patent uses periodic action by implementing a sequence of test patterns where each pattern serves a specific diagnostic purpose. The first test pattern detects the presence of faults, and subsequent patterns with modified control data localize the specific faulty flop. This structured periodic approach balances testing time investment with progressive fault localization capability.
Solution Approach 2:
The patent applies preliminary action by first generating a test pattern that detects fault presence before attempting full localization. The initial test pattern with specific control data identifies whether faults exist, and only then are additional patterns generated for localization, avoiding unnecessary testing time while maintaining diagnostic capability.
Data Source
AI summary
A method for localizing at least one scan flop associated with a fault in an integrated circuit. A first test pattern, including a first scan-in data and first control data, is generated. Based on the first control data of the first test pattern, a first fault data is generated by applying the first scan-in data of the first test pattern to scan flops in a test circuit of the integrated circuit. If the first fault data indicates that a fault may be present in the integrated circuit, a second test pattern, including a second scan-in data and a second control data is generated.


