Scan Frame Based Test Access Mechanisms for IC Testing Efficiency
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Solution Overview
Problem
Conventional scan testing methods for electrical circuits are inefficient and do not effectively utilize scan framing techniques to improve testing processes.
Innovation Solution
The introduction of Test Access Mechanism (TAM) circuits that employ a scan framing technique for inputting and outputting scan test data to and from core scan paths, utilizing Stimulus & Compress, Stimulus & Maskable Compress, Decompress & Compress, and Decompress & Maskable Compress TAMs to enhance testing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scan testing methods are used, then testing can be performed, but test time and cost are excessive and efficiency is low
Solution Approach 1:
The patent segments the scan testing process into distinct functional blocks (stimulus decompressor, response compactor, scan frame controller) that can operate independently and in parallel. This segmentation allows simultaneous stimulus application and response collection across multiple scan paths, dramatically improving testing efficiency and reducing overall test time.
Solution Approach 2:
The patent introduces a temporal dimension to scan testing by implementing scan frames with multiple sub-frames. Each sub-frame can be configured to test different portions of the circuit at different times, allowing comprehensive testing to be completed in fewer clock cycles. This multi-dimensional approach to test data organization and application significantly reduces test time while maintaining thoroughness.
2Adaptability or versatility
If more test signals are used between tester and die/IC, then more comprehensive testing is possible, but the number of required test signals increases complexity
Solution Approach 1:
The patent merges multiple test signal functions into consolidated test access mechanisms. The scan frame controller integrates stimulus generation, timing control, and response collection into a unified structure that operates through a limited set of standardized test signals. This merging maintains comprehensive testing capability while reducing the number of separate test signals required between tester and die/IC.
Solution Approach 2:
The patent implements universal test access mechanisms that can perform multiple testing functions through a standardized interface. The scan frame structure and controller are designed to handle various test configurations (different numbers of scan paths, different test patterns, different response collection methods) using the same basic test signals, thereby reducing complexity while maintaining versatility.
3Speed
If scan framing techniques are not used, then conventional testing proceeds, but testing efficiency and speed are limited
Solution Approach 1:
The patent implements preliminary action by pre-configuring scan frames with multiple sub-frames before actual testing begins. The scan frame controller is pre-loaded with timing and control information that enables rapid sequential testing across multiple scan paths without requiring complex real-time decision-making. This pre-preparation significantly increases testing speed while keeping the control mechanism manageable.
Solution Approach 2:
The patent introduces a scan frame controller as an intermediary between the tester and the scan paths. This intermediary manages the complexity of high-speed multi-path testing by providing a standardized control interface and handling the coordination of multiple scan paths internally. The intermediary absorbs the complexity, allowing the overall system to achieve high testing speed without proportionally increasing external interface complexity.
Data Source
AI summary
Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.