Scan Isolation Multiplexer Architecture for Silicon Area Reduction
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Solution Overview
Problem
Current scan isolation and bypass architectures for integrated circuit devices require significant silicon area due to the need for state elements and multiplexers at each input and output, which becomes impractical for devices with a large number of pins.
Innovation Solution
A scan isolation and bypass architecture that uses input and output isolation multiplexers, along with AND logic and exclusive-OR logic, to selectively route signals and reduce the number of functional inputs and outputs, eliminating the need for state elements and minimizing silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a state element and multiplexer are added for each input and output of the embedded core, then scan isolation feedback and bypass testing can be implemented, but silicon area increases significantly
Solution Approach 1:
The patent merges the functionality of multiple state elements into a single shared state element that serves all inputs and outputs of the embedded core. Instead of having separate state elements for each input/output pair, the invention combines their functions into one centralized state element that can be selectively configured to isolate different portions of the circuit during testing.
Solution Approach 2:
The shared state element is designed to perform multiple functions: it can isolate the embedded core from external logic for core testing, isolate external logic from the core for external logic testing, and support both feedback and bypass testing modes. This multi-functional approach eliminates the need for dedicated state elements for each specific testing scenario.
2Adaptability or versatility
If the number of inputs and outputs of the embedded core increases, then the core can handle more complex functionality, but the silicon area required for scan isolation circuitry increases
Solution Approach 1:
The patent applies merging by consolidating all input isolation multiplexers and output isolation multiplexers into shared resources. Instead of having dedicated isolation circuitry for each input and output pin, the invention uses a pool of shared multiplexers that can be dynamically allocated to different inputs and outputs based on testing requirements.
Solution Approach 2:
The isolation architecture employs dynamic configuration through control signals that redirect the functionality of shared multiplexers and state elements based on the specific testing needs. The system can dynamically reconfigure which inputs and outputs are isolated during different testing phases, allowing the same hardware resources to adapt to varying numbers of inputs and outputs.
Data Source
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AI summary
A feedback scan isolation and bypass architecture apparatus and method. The apparatus includes core logic, and input and output multiplexers. The input multiplexer selectively provides a functional input or the core output to the core input based on a test signal. The output multiplexer selectively provides the core output or the input multiplexer output to a functional output based on the test signal. When the test signal indicates core feedback testing, the output multiplexer outputs the core output and the input multiplexer feeds back the core output to the core input. When the test signal indicates bypass testing, the input multiplexer outputs the functional input and the output multiplexer outputs the functional input bypassing the core logic. Logic can block the feedback or bypass signals when there are timing issues. Logic can modify the number of feedback or bypass signals when the number of functional inputs and outputs are different.