Scan Line Driving Circuit Self-Generated Gate Voltage
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Solution Overview
Problem
Existing scan line driving circuits for electro-optical devices require a high voltage threshold to activate transistors, leading to increased complexity and power supply breakdown voltage, as well as potential display quality issues due to penetration current and half-ON states.
Innovation Solution
A scan line driving circuit that uses a demultiplexer system with unit circuits for each row of scan lines, where a first transistor is self-generated with a gate voltage using active and non-active levels, and a short-circuiting circuit prevents half-ON states by short-circuiting parasitic capacitors, simplifying the structure and improving display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a demultiplexer system with transistors as switches is used to drive scan lines, then the scan lines can be activated in turn by block selection, but a voltage higher than the active level by a threshold voltage or more must be applied to turn on the transistors, requiring separate high voltage generation and increasing power supply breakdown voltage and structural complexity
Solution Approach 1:
The gate voltage for the first transistor is self-generated by utilizing the active level and non-active level signals already present in the system. The second transistor acts as a voltage amplifier that generates the required gate voltage from the logical signal, eliminating the need for external high voltage generation circuits and reducing power supply breakdown voltage requirements
Solution Approach 2:
The second transistor serves as an intermediary voltage amplifier between the logical signal source and the first transistor gate. It converts the logical signal into a sufficient gate voltage to turn on the first transistor without requiring external high voltage sources, thus simplifying the power supply circuit
2Ease of operation
If transistors are used as switches in the demultiplexer system, then block selection and sequential activation is achieved, but penetration current flows when electrical properties of p-channel and n-channel transistors are not harmonized, degrading display quality
Solution Approach 1:
The short-circuiting circuit is activated in advance to discharge the parasitic capacitor before the first transistor turns on. This preliminary action prevents the half-ON state and associated penetration current by ensuring the gate voltage transitions cleanly without residual charge that would cause unwanted current flow
3Device complexity
If the gate voltage of the first transistor is not properly controlled, then the transistor may enter a half-ON state due to parasitic capacitor influence, but this causes off-leak current in pixel transistors and deteriorates display quality
Solution Approach 1:
The parasitic capacitor, which normally causes harmful half-ON states and off-leak currents, is converted into a beneficial element by using it as the target for the short-circuiting circuit. The discharge path through the short-circuiting circuit transforms the harmful charge storage into a controlled reset mechanism that prevents display quality deterioration
Data Source
AI summary
Each scan line 112 has a unit circuit 40 that has TFTs 62,64 and 66. Capacitance C1 is short-circuited by the TFTs. Reset signal Rst is supplied to the gate electrode of TFT 62. the source electrode of TFT 62 is connected to a gate-on power supply line Vgon. The gate electrode of TFT 66 is connected to the drain electrodes of TFT 62 and 64, and the drain electrode of TFT 66 is connected to the gate electrode of TFT 42. The source electrodes of TFT 64 and 66 are connected to their own scan lines 112.