Display Scan Line Parallel Branch Layout for Lower Impedance
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Solution Overview
Problem
Existing electronic devices face challenges in achieving optimal display performance due to high impedance in the driving layer, which affects signal transmission and quality.
Innovation Solution
The electronic device incorporates a driving layer with a scan line that includes parallel branches, reducing overall impedance by electrically connecting two branches on opposite sides of an opening, and a semiconductor layer with dual gates, which alleviates the resistance-capacitance delay effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional scan line structure is used, then the device complexity is low, but the impedance is high which deteriorates signal transmission quality
Solution Approach 1:
The scan line is divided into multiple segments (first scan line segment and second scan line segment) that are electrically connected in parallel. This segmentation reduces the overall impedance of the scan line while maintaining a relatively simple structural configuration, thereby improving signal transmission quality without excessively increasing device complexity.
2Reliability
If the scan line impedance is reduced by adding parallel branches, then the signal transmission quality improves, but the manufacturing precision requirements increase
Solution Approach 1:
The first scan line segment and second scan line segment are merged into a single scan line structure through electrical parallel connection. This merging approach allows the impedance reduction benefit while consolidating the manufacturing process, as both segments can be formed using the same thin film transistor fabrication techniques, thereby managing manufacturing precision requirements.
3Ease of manufacture
If a single-layer scan line is used, then the ease of manufacture is high, but the impedance reduction capability is limited
Solution Approach 1:
The scan line structure transitions from a single-layer configuration to a multi-segment parallel configuration, effectively adding a dimensional aspect to the electrical connection. This allows impedance reduction through parallel pathways while maintaining fabrication simplicity, as the additional segments are integrated into the existing thin film transistor manufacturing process without requiring separate fabrication steps.
Data Source
AI summary
An electronic device of an embodiment of the disclosure includes a first substrate, a second substrate, and a driving layer. The first substrate and the second substrate are disposed opposite to each other, and the driving layer is disposed between the first substrate and the second substrate. The driving layer includes a scan line and a data line. The scan line is disposed on the first substrate and includes a first scan line segment. The first scan line segment has an opening and includes a first branch and a second branch. The first branch and the second branch are located on two opposite sides of the opening and are electrically connected in parallel with each other. The data line is disposed on the first substrate and intersects with the scan line. The electronic device of the embodiment of the disclosure may exhibit ideal display effect.