Scan Line Pulse Circuit Layout for Synchronized Transistor Switching
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Solution Overview
Problem
In large active matrix display devices, increased wiring resistance and parasitic capacitance in scan lines lead to time lags in switching transistors, causing potential differences and incorrect image signal input, particularly when transistors turn off at different times.
Innovation Solution
Inputting a non-selection signal from both ends of the scan line simultaneously with a selection signal, using transistors with clock signals to synchronize the potential changes and ensure uniform switching of connected transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the scan line extends along a plurality of pixels arranged in a specific row, then the scan line can control switching of transistors in each pixel, but the total length of the scan line is necessarily increased and wiring resistance is easily increased
Solution Approach 1:
The scan line is divided into multiple segments, each controlled by a separate scan line driver circuit. The display device is divided into multiple regions (first region and second region), with each region having its own scan line driver circuit that controls scan lines for transistors in that region. This segmentation reduces the effective length of each scan line segment, thereby reducing wiring resistance while maintaining comprehensive transistor control capability.
2Ease of operation
If the scan line intersects with a plurality of signal lines, then the scan line can deliver selection signals to multiple pixels, but parasitic capacitance generated at intersections with the signal lines is added to the scan line
Solution Approach 1:
By segmenting the scan line control into multiple independent scan line driver circuits, each controlling a specific region, the parasitic capacitance effect is localized to smaller segments. This reduces the cumulative parasitic capacitance impact on signal integrity while maintaining the ability to deliver selection signals to multiple pixels through coordinated operation of segmented driver circuits.
3Productivity
If the display device is increased in size and the number of pixels is increased, then the display device can provide higher resolution, but the total length of the scan line is further increased and the number of signal lines intersecting with the scan line is increased
Solution Approach 1:
The display device is divided into multiple regions with each region having its own scan line driver circuit. This allows high-resolution displays to be achieved by increasing the number of regions and pixels per region, while each individual scan line segment maintains a manageable length that limits wiring resistance and parasitic capacitance effects.
Solution Approach 2:
Instead of simply extending scan lines horizontally across the entire display, the patent introduces a vertical dimension by stacking multiple scan line driver circuits and their associated scan lines in different regions. This multi-dimensional approach allows high pixel counts to be achieved without proportionally increasing individual scan line lengths.
4Productivity
If the wiring resistance and the parasitic capacitance are increased, then the scan line can cover more pixels, but the time lag is increased in proportion to the wiring resistance and the parasitic capacitance
Solution Approach 1:
By dividing the display into multiple regions with separate scan line driver circuits, the time lag is reduced in each segment. Although more driver circuits are needed for larger displays, each individual scan line segment experiences minimal time lag, ensuring synchronized transistor switching across all regions when driver circuits are coordinated properly.
Data Source
AI summary
A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.