Scan Logic for Mixed Latch Flip-Flop Circuits
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Solution Overview
Problem
Testing circuits with a mix of latches and flip-flops is challenging due to differences in their sensitivity and operation, leading to inefficient test coverage and debugging difficulties, especially when phased clocks are used, causing multiple latches to be loaded with the same data and making it hard to control test vectors effectively.
Innovation Solution
A system that interleaves flip-flops with latches and uses multiplexers to propagate scan data, allowing scan logic to control the loading of test data into both flip-flops and latches, enabling separate clock signals and enable signals for efficient testing, and utilizing flip-flops as lock-up latches to assist latches in shifting and capturing data with minimal overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If latches are used in the circuit, then area is reduced and timing is improved, but testability deteriorates due to level-sensitive operation and difficulty in controlling test vectors
Solution Approach 1:
A scan chain is introduced as an intermediary structure to control and propagate test vectors through the circuit. The scan chain includes scan latches and scan flip-flops that mediate the testing process, allowing sequential loading of test vectors and controlled propagation through the circuit under test, thereby improving testability while maintaining the benefits of level-sensitive latches in the main circuit path
2Ease of operation
If phased clocks are used to control latches, then timing control is improved, but multiple latches are loaded with the same data making it hard to control test vectors
Solution Approach 1:
The testing process is segmented into distinct phases: loading test vectors into the scan chain, propagating them through the circuit under test, capturing results, and shifting out the scan chain. This segmentation allows independent control of each phase, preventing the problem where multiple latches are loaded with the same data simultaneously. Each latch in the scan chain can be controlled independently through the scan enable signal, improving ease of operation while maintaining efficient testing time
3Adaptability or versatility
If latches and flip-flops are mixed in the circuit, then functionality is improved, but device complexity increases due to different sensitivity requirements
Solution Approach 1:
The scan chain is designed with universal multiplexers that can interface with both latches and flip-flops. These multiplexers can be configured to work with level-sensitive latches or edge-triggered flip-flops, providing a universal interface for the scan logic. This multi-functionality allows the same scan logic to control mixed latch and flip-flop circuits without requiring separate control mechanisms for each element type, thereby improving circuit functionality while limiting the increase in scan logic complexity
Data Source
AI summary
Embodiments of the present disclosure may include a system for scanning a circuit, the embodiments including flip-flops, latches interleaved between the flip-flops, multiplexers configured to propagate scan data between the flip-flops and latches, and scan logic configured to control the multiplexers to load test data into the flip-flops and latches. A first pair of latches are interleaved between a first pair of flip-flops.