Scan Asynchronous Memory Element for Muller C-Element Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for enhancing the testability of asynchronous semiconductor integrated circuits, such as those using scan methods, often result in increased circuit area and signal delay overheads, and fail to completely test asynchronous memory elements like Muller's C-element due to input/output dependencies between L1 and L2 latches in L1L2* single latch designs, leading to incomplete testing and potential oscillation issues.
Innovation Solution
The introduction of a scan asynchronous memory element with a scan control logic circuit that allows for the generation of n-input signals from n-bit signal inputs and scan inputs, enabling the asynchronous memory element to hold a current state based on specific bit patterns, and the cascade connection of these elements in a semiconductor integrated circuit to minimize overhead and ensure complete testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If a scan flip-flop is inserted in the feedback path of an asynchronous memory element to form a shift register, then testability is enhanced, but circuit area overhead and signal delay overhead increase
Solution Approach 1:
The patent merges the scan flip-flop with the asynchronous memory element (C-element) by sharing the feedback path and utilizing the same internal nodes. The scan flip-flop's Q output is connected to the C-element's feedback input, and the C-element's output feeds back to the scan flip-flop's D input through a multiplexer. This integration allows the scan functionality to be embedded within the existing memory element structure rather than adding separate components, thereby reducing circuit area overhead while maintaining enhanced testability.
2Difficulty of detecting and measuring
If a scan flip-flop is inserted in the feedback path of an asynchronous memory element to form a shift register, then testability is enhanced, but signal delay overhead increases
Solution Approach 1:
The patent implements preliminary action by using the scan flip-flop to pre-load test patterns into the asynchronous memory element before actual operation. The scan flip-flop captures and holds the test pattern in its internal state, which is then transferred to the C-element through controlled signal transitions. This preliminary loading allows the test pattern to be prepared and staged before being applied to the asynchronous circuit, reducing the overall signal delay required for complete testing compared to direct sequential loading.
3Area of stationary object
If L1L2* single latch design is used to reduce circuit area overhead, then area is reduced, but complete testing of asynchronous memory elements cannot be achieved due to input/output dependency between L1 and L2 latches
Solution Approach 1:
The patent introduces an intermediary multiplexer in the feedback path between the C-element and the scan flip-flop. This multiplexer acts as a mediator that selectively connects either the C-element output or a forced logic level to the scan flip-flop input based on the scan enable signal. During normal operation, the multiplexer transparently passes the C-element output. During testing, the multiplexer can force specific logic levels to break the direct input/output dependency between the L1 and L2 latches, enabling complete testing of the asynchronous memory element while maintaining the area-efficient L1L2* single latch structure.
Data Source
AI summary
A scan asynchronous memory element includes: an asynchronous memory element configured to receive an n-input; and a scan control logic circuit configured to generate an n-bit signal input and the n-input to the asynchronous memory element from a scan input. The scan control logic circuit outputs the signal input when a control signal supplied to the scan control logic circuit has a first bit pattern, the scan control logic circuit outputs the scan input when the control signal has a second bit pattern, and the scan control logic circuit outputs a bit pattern allowing the asynchronous memory element to hold a previous value when the control signal has a bit pattern other than the first and second bit patterns.